参数资料
型号: AD7294BCPZRL
厂商: Analog Devices Inc
文件页数: 29/49页
文件大小: 0K
描述: IC ADC 12BIT I2C/SRL 1M 56LFCSP
标准包装: 2,500
类型: ADC,DAC
分辨率(位): 12 b
采样率(每秒): 22.22k
数据接口: I²C,串行
电压电源: 模拟和数字
电源电压: 4.4 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 56-VFQFN 裸露焊盘,CSP
供应商设备封装: 56-LFCSP-VQ(8x8)
包装: 带卷 (TR)
AD7294
Data Sheet
Rev. H | Page 34 of 48
I2C INTERFACE
GENERAL I2C TIMING
Figure 50 shows the timing diagram for general read and write
operations using an I2C-compliant interface.
The I2C bus uses open-drain drivers; therefore, when no device
is driving the bus, both SCL and SDA are high. This is known as
idle state. When the bus is idle, the master initiates a data transfer
by establishing a start condition, defined as a high-to-low
transition on the serial data line (SDA) while the serial clock line
(SCL) remains high. This indicates that a data stream follows. The
master device is responsible for generating the clock.
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter followed by an acknowledge bit (ACK)
from the receiver. Data transitions on the SDA line must occur
during the low period of the clock signal and remain stable
during the high period. The receiver should pull the SDA line
low during the acknowledge bit to signal that the preceding byte
has been received correctly. If this is not the case, cancel the
transaction.
The first byte that the master sends must consist of a 7-bit slave
address, followed by a data direction bit. Each device on the bus
has a unique slave address; therefore, the first byte sets up
communication with a single slave device for the duration of the
transaction.
The transaction can be used either to write to a slave device
(data direction bit = 0) or to read data from it (data direction
bit = 1). In the case of a read transaction, it is often necessary
first to write to the slave device (in a separate write transaction)
to tell it from which register to read. Reading and writing
cannot be combined in one transaction.
When the transaction is complete, the master can keep control
of the bus, initiating a new transaction by generating another
start bit (high-to-low transition on SDA while SCL is high). This
is known as a repeated start (Sr). Alternatively, the bus can be
relinquished by releasing the SCL line followed by the SDA line.
This low-to-high transition on SDA while SCL is high is known
as a stop bit (P), and it leaves the I2C bus in its idle state (no
current is consumed by the bus).
The example in Figure 50 shows a simple write transaction
with an AD7294 as the slave device. In this example, the
AD7294 register pointer is being set up ready for a future read
transaction.
P7
P6
P5
P4
P3
P2
P1
P0
START COND
BY MASTER
ACK. BY
AD7294
SLAVE ADDRESS BYTE
ACK. BY
AD7294
SCL
SDA
REGISTER ADDRESS
STOP BY
MASTER
USER PROGRAMMABLE 5 LSBs
R/W
A6
A5
A4
A3
A2
A1
A0
05747-
040
Figure 50. General I2C Timing
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