参数资料
| 型号： | AD7294BCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/49页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT I2C/SRL 1M 56LFCSP |
| 标准包装： | 2,500 |
| 类型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 22.22k |
| 数据接口： | I²C，串行 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 4.4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 56-LFCSP-VQ（8x8） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD7294
Rev. H | Page 39 of 48
MODES OF OPERATION
There are two different methods of initiating a conversion on
the AD7294: command mode and autocycle mode.
COMMAND MODE
In command mode, the AD7294 ADC converts on-demand on
either a single channel or a sequence of channels. To enter this
mode, the required combination of channels is written into the
command register (0x00). The first conversion takes place at the
end of this write operation, in time for the result to be read out
in the next read operation. While this result is being read out,
the next conversion in the sequence takes place, and so on.
To exit the command mode, the master should not acknowledge
the final byte of data. This stops the AD7294 transmitting,
allowing the master to assert a stop condition on the bus. It is
therefore important that, after writing to the command register,
a repeated start (Sr) signal be used rather than a stop (P) followed
by a start (S) when switching to read mode; otherwise, the
command mode exits after the first conversion.
After writing to the command register, the register pointer is
returned to its previous value. If a new pointer value is required
(typically the ADC Result Register 0x01), it can be written
immediately following the command byte. This extra write
operation does not affect the conversion sequence because the
second conversion triggers only at the start of the first read
operation.
The maximum throughput that can be achieved using this
mode with a 400 kHz I2C clock is (400 kHz/18) = 22.2 kSPS.
Figure 56 shows the command mode converting on a sequence
of channels including VIN0, VIN1, and ISENSE1.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device (AD7294) asserts an
acknowledge on SDA.
4. The master sends the Command Register Address 0x00.
The slave asserts an acknowledge on SDA.
5. The master sends the Data Byte 0x13 which selects the
VIN0, VIN1, and ISENSE1 channels.
6. The slave asserts an acknowledge on SDA.
7. The master sends the result register address (0x01). The
slave asserts an acknowledge on SDA.
8. The master sends the 7-bit slave address followed by the
write bit (high).
9. The slave (AD7294) asserts an acknowledge on SDA.
10. The master receives a data byte, which contains the
alert_flag bit, the channel ID bits, and the four MSBs of the
converted result for Channel VIN0. The master then asserts
an acknowledge on SDA.
11. The master receives the second data byte, which contains
the eight LSBs of the converted result for Channel VIN0.
The master then asserts on acknowledge on SDA.
12. Point 10 and Point 11 repeat for Channel VIN1 and
Channel ISENSE1.
13. Once the master has received the results from all the
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Point 10 to Point 12 are repeated.
14. The master asserts a no acknowledge on SDA and a stop
condition on SDA to end the conversion and exit
command mode.
The AD7294 automatically exits command mode if no read
occurs in a 5 ms period. To change the conversion sequence,
rewrite a new sequence to the command mode.
05747-
056
S
A
P
...
0
A
COMMAND = 0x13
A
VIN0<11:8>
A
POINT TO RESULT REG (0x01)
SR
1
A
*
A
CH ID (000)
ALERT?
...
A
CH ID (001)
ALERT?
A
...
A
ISENSE1<11:8>
*
A
...
A
VIN0<7:0>
...
........
A
* = POSITION OF A CONVERSION START
SLAVE ADDRESS
POINT TO COMMAND REG (0x00)
VIN1<7:0>
VIN0<7:0>
VIN1<11:8>
VIN0<11:8>
SLAVE ADDRESS
ISENSE1<7:0>
ALERT?
CH ID (100)
ALERT?
CH ID (000)
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
Figure 56. Command Mode Operation
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