参数资料
| 型号： | AD9548BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/112页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 产品变化通告： | AD9548 Mask Change 20/Oct/2010 |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 88-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 88-LFCSP-VQ（12x12） |
| 包装： | 托盘 |
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AD9548
Data Sheet
Rev. E | Page 16 of 112
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
21, 22
AVDD3
I
Power
3.3 V Analog (DAC) Power Supply.
23, 24
AVDD
I
Power
1.8 V Analog (DAC) Power Supply.
26
CLKINN
I
Differential
input
Clock Distribution Input. In standard operating mode, this pin is connected to the
filtered DACOUTN output. This internally biased input is typically ac-coupled and,
when configured as such, can accept any differential signal whose single-ended
swing is at least 400 mV.
27
CLKINP
I
Differential
input
Clock Distribution Input. In standard operating mode, this pin is connected to the
filtered DACOUTP output
29
AVDD
I
Power
1.8 V Analog (Input Receiver) Power Supply.
30
OUT_RSET
O
Current set
resistor
Connect an optional 3.12 k resistor from this pin to ground (see the Output
31, 37, 38,
44
AVDD3
I
Power
Analog Supply for Output Driver. These pins are normally 3.3 V but can be 1.8 V.
Pin 31 powers Out0x. Pin 37 powers OUT1x. Pin 38 powers OUT2x. Pin 44 powers
OUT3x. Apply power to these pins even if the corresponding outputs (OUT0P/
OUT0N, OUT1P/ OUT1N, OUT2P/ OUT2N, and OUT3P/ OUT3N) are not used. See
the Power Supply Partitions section.
32
OUT0P
O
LVPECL,
LVDS, or
CMOS
Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS.
LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS
operation can be either 1.8 V or 3.3 V, depending on the output driver power
supply.
33
OUT0N
O
LVPECL,
LVDS, or
CMOS
Complementary Output 0. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
34, 41
AVDD
I
Power
1.8 V Analog (Output Divider) Power Supply.
35
OUT1P
O
LVPECL,
LVDS, or
CMOS
Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS.
LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS
operation can be either 1.8 V or 3.3 V, depending on the output driver power
supply.
36
OUT1N
O
LVPECL,
LVDS, or
CMOS
Complementary Output 1. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
39
OUT2P
O
LVPECL,
LVDS, or
CMOS
Output 2. This output can be configured as LVPECL, LVDS, or single-ended CMOS.
LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS
operation can be either 1.8 V or 3.3 V, depending on the output driver power
supply.
40
OUT2N
O
LVPECL,
LVDS, or
CMOS
Complementary Output 2. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
42
OUT3P
O
LVPECL,
LVDS, or
CMOS
Output 3. This output can be configured as LVPECL, LVDS, or single-ended CMOS.
LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS
operation can be either 1.8 V or 3.3 V, depending on the output driver power
supply.
43
OUT3N
O
LVPECL,
LVDS, or
CMOS
Complementary Output 3. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
47
AVDD3
I
Power
3.3 V Analog (System Clock) Power Supply.
48
SYSCLK_VREG
I
System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from this
pin to ground. This pin is also the ac ground reference for the integrated SYSCLK
PLL multiplier’s external loop filter (see the SYSCLK PLL Multiplier section).
49
SYSCLK_LF
O
System Clock Multiplier Loop Filter. When using the frequency multiplier to drive
the system clock, an external loop filter can be attached to this pin.
50, 55
AVDD
I
Power
1.8 V Analog (System Clock) Power Supply.
52
SYSCLKN
I
Differential
input
Complementary System Clock Input. Complementary signal to SYSCLKP. SYSCLKN
contains internal dc biasing and should be ac-coupled with a 0.01 μF capacitor,
except when using a crystal, in which case connect the crystal across SYSCLKP
and SYSCLKN.
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