参数资料
| 型号： | AD9548BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/112页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 88LFCSP |
| 产品变化通告： | AD9548 Mask Change 20/Oct/2010 |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750kHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 88-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 88-LFCSP-VQ（12x12） |
| 包装： | 托盘 |
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Data Sheet
AD9548
Rev. E | Page 103 of 112
Table 145. EEPROM Storage Sequence for General Configuration Settings
Address
Bits
Bit Name
Description
0x0E15
[7:0]
General
The default value of this register is 0x14, which the controller interprets as a data
instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of
data (20 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x14 in the EEPROM and increments the EEPROM address pointer.
0x0E16
[7:0]
General
The default value of these two registers is 0x0200. Note that Register 0x0E16 and
Register 0x0E17 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0200). The controller
stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 21 bytes from the register map (beginning at Address 0x0200) to the
EEPROM and increments the EEPROM address pointer by 22 (21 data bytes and
one checksum byte). The 21 bytes transferred correspond to the general
configuration parameters in the register map.
0x0E17
[7:0]
Table 146. EEPROM Storage Sequence for DPLL Settings
Address
Bits
Bit Name
Description
0x0E18
[7:0]
DPLL
The default value of this register is 0x1B, which the controller interprets as a data
instruction. Its decimal value is 27, which tells the controller to transfer 28 bytes
of data (27 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x1B in the EEPROM and increments the EEPROM address pointer.
0x0E19
[7:0]
DPLL
The default value of these two registers is 0x0300. Note that Register 0x0E19 and
Register 0x0E1A are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0300). The controller
stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 28 bytes from the register map (beginning at Address 0x0300) to the
EEPROM and increments the EEPROM address pointer by 29 (28 data bytes and
one checksum byte). The 28 bytes transferred correspond to the DPLL parameters
in the register map.
0x0E1A
[7:0]
Table 147. EEPROM Storage Sequence for Clock Distribution Settings
Address
Bits
Bit Name
Description
0x0E1B
[7:0]
Clock distribution
The default value of this register is 0x19, which the controller interprets as a data
instruction. Its decimal value is 25, which tells the controller to transfer 26 bytes of
data (25 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x19 in the EEPROM and increments the EEPROM address pointer.
0x0E1C
[7:0]
Clock distribution
The default value of these two registers is 0x0400. Note that Register 0x0E1C and
Register 0x0x0E1D are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0400). The controller
stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 26 bytes from the register map (beginning at Address 0x0400) to the
EEPROM and increments the EEPROM address pointer by 27 (26 data bytes and
one checksum byte). The 26 bytes transferred correspond to the clock distribution
parameters in the register map.
0x0E1D
[7:0]
0x0E1E
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O
update instruction. The controller stores 0x80 in the EEPROM and increments the
EEPROM address pointer.
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