参数资料
| 型号： | AD9558BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/104页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 产品变化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 4:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
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AD9558
Data Sheet
Rev. B | Page 38 of 104
CLOCK DISTRIBUTION
FROM APLL
(3.35GHz TO 4.05GHz)
09758-
139
÷M1
OUT11
OUT21
MAX
1.25GHz
MAX
1.25GHz
÷M2
RF
DIVIDER 1
÷3 TO ÷11
RF
DIVIDER 2
÷3 TO ÷11
FRAME SYNC
MODE ONLY
÷M0
OUT01
÷M3
OUT41
OUT31
÷M3b
OUT51
×2
OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz.
CHANNEL
SYNC
BLOCK
FRAME
SYNC
BLOCK
CHIP RESET
SELECTED INPUT FRAME PULSE
SYNC SIGNAL TO
M0 TO M3 DIVIDERS
FRAME SYNC
FRAME SYNC ENGAGED SIGNAL
FRAME
SYNC
MONITOR
SYNC/SOFT_SYNC
Fsync_ALIGN_METHOD
Figure 40. Clock Distribution Block Diagram
CLOCK DIVIDERS
The channel divider blocks, M0, M1, M2, M3, and M3b, are
10-bit integer dividers with a divide range of 1 to 1023. The
channel divider block contains duty cycle correction that
guarantees 50% duty cycle for both even and odd divide ratios.
OUTPUT POWER-DOWN
The output drivers can be individually powered down.
OUTPUT ENABLE
Each of the output channels offers independent control of enable/
disable functionality via the distribution enable register. The
distribution outputs use synchronization logic to control
enable/disable activity to avoid the production of runt pulses
and ensure that outputs with the same divide ratios become
active/inactive in unison.
OUTPUT MODE
The user has independent control of the operating mode of each of
the four output channels via the output clock distribution registers
(Address 0x0500 to Address 0x0515). The operating mode
control includes
Logic family and pin functionality
Output drive strength
Output polarity
Divide ratio
Phase of each output channel
Channel 0 and Channel 3 provide 3.3 V CMOS, in addition
to 1.8 V CMOS modes. Channel 1 and Channel 2 have 1.8 V
CMOS, LVDS, and HSTL modes.
All CMOS drivers feature a CMOS drive strength that allows
the user to choose between a strong, high performance CMOS
driver, or a lower power setting with less EMI and crosstalk.
The best setting is application dependent.
For applications where LVPECL levels are required, the user
should choose the HSTL mode, and ac-couple the output signal.
See the Input/Output Termination Recommendations section
for recommended termination schemes.
CLOCK DISTRIBUTION SYNCHRONIZATION
Divider Synchronization
The dividers in the clock distribution channels can be
synchronized with each other.
At power-up, the clock dividers are held static until a sync signal
is initiated by the channel SYNC block. The following are
possible sources of a SYNC signal, and these settings are found
in Register 0x0500:
Direct sync via Bit 2 of Register 0x0500
Direct sync via a sync op code (0xA1) in the EEPROM
storage sequence during EEPROM loading
DPLL phase or frequency lock
A rising edge of the selected reference input
The
A
SYNCE
A
pin
A multifunction pin configured for the SYNC signal
The APLL lock detect signal gates the SYNC signal from the
channel sync block shown in Figure 40. The channel dividers
receive a SYNC signal from the channel SYNC block only if the
APLL is calibrated and locked, unless the APLL locked
controlled sync bit (Register 0x0405[3]) is set.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| AD9559 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:时钟和定时器开发工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| AD9559BCPZ | 功能描述:时钟发生器及支持产品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:时钟发生器及支持产品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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