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参数资料
| 型号： | AD9785-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9785 |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 800M |
| 数据接口： | 串行 |
| 设置时间： | 22ms |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，缆线，CD |
| 已用 IC / 零件： | AD9785 |
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AD9785/AD9787/AD9788
Rev. A | Page 24 of 64
SPI REGISTER MAP
When reading Table 9, note that the AD9785/AD9787/AD9788 is a 32-bit part and, therefore, the 4th through the 11th columns (beginning
with the MSB and ending with the LSB) represent a set of eight bits. Refer to the Bit Range column for the actual bits being described.
Table 9.
Address
Register
Name
Bit
Range
MSB
MSB 1
MSB 2
MSB 3
MSB 4
MSB 5
MSB 6
LSB
Default
0x00
Comm.
(COMM)
Register
[7:0]
SPI_SDIO
bidirectional
(active high,
3-wire)
LSB first
Software
reset
Power-
down
mode
Auto
power-
down
enable
I/O
transfer
(self-
reset)
Automatic
I/O
transfer
enable
Open
0x02
0x01
Digital
Control
Register
[7:0]
Interpolation Factor [1:0]
Data
format
Single-
port
mode
Real
mode
IQ select
invert
Q first
Modulator
gain
control
0x00
[15:8]
Reserved
Clear phase
accumulator
PN code
sync
enable
Sync
mode
select
Pulse
sync
enable
Reserved
Inverse
sinc
enable
DATACLK
output
enable
0x31
0x02
Data Sync
Control
Register
[7:0]
Data Timing
Margin [0]
LVDS data
clock enable
DATACLK
invert
DATACLK
delay
enable
Data
timing
mode
Set high
Data sync
polarity
Reserved
0x00
[15:8]
DATACLK Delay [4:0]
Data Timing Margin [3:1]
0x00
0x03
Multichip
Sync
Control
Register
[7:0]
Clock State [3:0]
Sync Timing Margin [3:0]
0x00
[15:8]
SYNC _O Delay [4:0]
Set high
SYNC_O
polarity
Sync
loopback
enable
0x00
[23:16]
SYNC_I Delay [4:0]
Sync
error
check
mode
Set low
DATACLK
input
0x00
[31:24]
Correlate Threshold [4:0]
SYNC _I
enable
SYNC _O
enable
Set low
0x80
0x04
PLL
Control
Register
[7:0]
PLL Band Select [5:0]
PLL VCO Drive [1:0]
0xCF
[15:8]
PLL enable
PLL VCO Divisor [1:0]
PLL Loop Divisor [1:0]
PLL Bias [2:0]
0x37
[23:16]
VCO Control Voltage [2:0]
PLL Loop Bandwidth [4:0]
0x38
0x05
I DAC
Control
Register
[7:0]
I DAC Gain Adjustment [7:0]
0xF9
[15:8]
I DAC sleep
I DAC
power-down
Reserved
I DAC Gain Adjustment
[9:8]
0x01
0x06
Auxiliary
DAC 1
Control
Register
[7:0]
Auxiliary DAC 1 Data [7:0]
0x00
[15:8]
Auxiliary
DAC 1 sign
Auxiliary
DAC 1
current
direction
Auxiliary
DAC 1
power-
down
Reserved
Auxiliary DAC 1 Data
[9:8]
0x00
0x07
Q DAC
Control
Register
[7:0]
Q DAC Gain Adjustment [7:0]
0xF9
[15:8]
Q DAC sleep
Q DAC
power-down
Reserved
Q DAC Gain Adjustment
[9:8]
0x01
0x08
Auxiliary
DAC 2
Control
Register
[7:0]
Auxiliary DAC 2 Data [7:0]
0x00
[15:8]
Auxiliary
DAC 2 sign
Auxiliary
DAC 2
current
direction
Auxiliary
DAC 2
power-
down
Reserved
Auxiliary DAC 2 Data
[9:8]
0x00
0x09
Interrupt
Control
Register
[7:0]
Data timing
error IRQ
Sync timing
error IRQ
Data
timing
error
type
Sync
timing
error
type
PLL lock
indicator
Reserved
Data port
IRQ enable
Sync port
IRQ
enable
0x00
[15:8]
Reserved
Clear lock
indicator
(self-
reset)
Sync
lock
lost
status
Sync lock
status
Reserved
0x00
0x0A
Frequency
Tuning
Word
Register
[31:0]
Frequency Tuning Word [31:0]
0x00
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相关代理商/技术参数 |
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|---|---|
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
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