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参数资料
| 型号： | AD9785-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9785 |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 800M |
| 数据接口： | 串行 |
| 设置时间： | 22ms |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，缆线，CD |
| 已用 IC / 零件： | AD9785 |
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AD9785/AD9787/AD9788
Rev. A | Page 36 of 64
DACCLK
REFCLK
INPUT
DATA
tSREFCLK
tHREFCLK
SYNC_I
tS_SYNC
tH_SYNC
07
09
8-
11
1
Figure 51. REFCLK 8×
OPTIMIZING THE DATA INPUT TIMING
The AD9785/AD9787/AD9788 have on-chip circuitry that
enables the user to optimize the input data timing by adjusting
the relationship between the DATACLK output and DCLK_SMP,
the internal clock that samples the input data. This optimization
is made by a sequence of SPI register read and write operations.
The timing optimization can be done under strict control of the
user, or the device can be programmed to maintain a configurable
timing margin automatically.
Figure 52 shows the circuitry that detects sample timing errors
and adjusts the data interface timing. The DCLK_SMP signal is
the internal clock used to latch the input data. Ultimately, it is
the rising edge of this signal that must be centered in the valid
sampling period of the input data. This is accomplished by
adjusting the time delay, tD, which changes the DATACLK
timing and, as a result, the arrival time of the input data with
respect to DCLK_SMP.
07
09
8
-06
1
TIMING
ERROR
IRQ
D
Q
D
CLK
DCLK_SMP
PD1[0]
DATACLK DELAY[4:0]
DATA
TIMING MARGIN[3:0]
DATACLK
TIMING
ERROR
TYPE
TIMING
ERROR
DETECTION
Δ
tD
Δ
tM
Δ
tM
Figure 52. Timing Error Detection and Optimization Circuitry
The error detection circuitry works by creating two sets of
sampled data (referred to as the margin test data) in addition to
the actual sampled data used in the device datapath. One set of
sampled data is latched before the actual data sampling point.
The other set of sampled data is latched after the actual data
sampling point. If the margin test data matches the actual data,
the sampling is considered valid and no error is declared. If
there is a mismatch between the actual data and the margin test
data, an error is declared.
The Data Timing Margin [3:0] variable (Register 0x02, Bits [10:7])
determines the amount of time before and after the actual data
sampling point the margin test data are latched. That is, the
Data Timing Margin [3:0] variable determines how much setup
and hold margin the interface needs for the data timing error
IRQ to remain inactive (to show error-free operation). There-
fore, the data timing error IRQ is set whenever the setup and
hold margins drop below the Data Timing Margin [3:0] value.
This does not necessarily indicate that the data latched into the
device is incorrect.
In addition to setting the data timing error IRQ, the data timing
error type bit (Register 0x09, Bit 5) is set when an error occurs.
The data timing error bit is set low to indicate a hold error and
high to indicate a setup error. Figure 53 shows a timing diagram
of the data interface and the status of the data timing error type bit.
07
09
8-
06
2
Δ
tM
Δ
tM
ACTUAL
SAMPLING
INSTANT
TIMING ERROR = 1,
DATA TIMING ERROR TYPE = 1
DATA TIMING ERROR = 1,
DATA TIMING ERROR TYPE = 0
DATA
TIMING ERROR = 0
DELAYED
DATA
SAMPLING
DELAYED
CLOCK
SAMPLING
Figure 53. Timing Diagram of Margin Test Data
Automatic Timing Optimization Mode
When the automatic timing optimization mode is enabled
(Register 0x02, Bit 3 = 1), the device continuously monitors the
timing error IRQ and timing error type bits. The DATACLK
Delay [4:0] value (Register 0x02, Bits [4:0]) increases if a setup
error is detected and decreases if a hold error is detected. The
value of the DATACLK Delay [4:0] setting currently in use can
be read back by the user.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSV | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80 |
| AD9786BSVRL | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP T/R |
| AD9786BSVZ | 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC+® 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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