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参数资料
| 型号： | AD9785-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/64页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9785 |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 800M |
| 数据接口： | 串行 |
| 设置时间： | 22ms |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，缆线，CD |
| 已用 IC / 零件： | AD9785 |
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AD9785/AD9787/AD9788
Rev. A | Page 33 of 64
INPUT DATA PORTS
The AD9785/AD9787/AD9788 can operate in two data input
modes: dual-port mode and single-port mode. In the default
dual-port mode (single-port mode = 0), each DAC receives data
from a dedicated input port. In single-port mode (single-port
mode = 1), both DACs receive data from Port 1. In single-port
mode, DAC 1 and DAC 2 data is interleaved and the TXENABLE
input is used to steer data to the intended DAC. In dual-port
mode, the TXENABLE input is used to power down the digital
datapath.
In dual-port mode, the data must be delivered at the input data
rate. In single-port mode, data must be delivered at twice the
input data rate of each DAC. Because the data inputs function up
to a maximum of 300 MSPS, it is only practical to operate with
input data rates up to 150 MHz per DAC in single-port mode.
In both dual-port and single-port modes, a data clock output
(DATACLK) signal is available as a fixed-time base with which
to drive data from an FPGA (field programmable gate array) or
from another data source. This output signal operates at the
input data rate. The DATACLK pin can operate as either an
input or an output.
SINGLE-PORT MODE
In single-port mode, data for both DACs is received on the
Port 1 input bus (P1D[15:0]). I and Q data samples are inter-
leaved and are latched on the rising edges of DATACLK.
Accompanying the data is the TXENABLE (Pin 39) input
signal, which steers incoming data to its respective DAC. When
TXENABLE is high, the corresponding data-word is sent to the
I DAC and, when TXENABLE is low, the corresponding data is
sent to the Q DAC. The timing of the digital interface in
interleaved mode is shown in Figure 48.
The Q first bit (Register 0x01, Bit 1) controls the pairing
order of the input data. With the Q first bit set to the default
of 0, the I/Q pairing sent to the DACs is the two input data-
words corresponding to TXENABLE low followed by
TXENABLE high.
With the Q first bit set to 1, the I/Q pairing sent to the DACs is
the two input data-words corresponding to TXENABLE high
followed by TXENABLE low. Note that with Q first set, the
I data still corresponds to the TXENABLE high word and the
Q data corresponds to the TXENABLE low word and only the
pairing order changes.
DUAL-PORT MODE
In dual-port mode, data for each DAC is received on the
respective input bus (P1D[15:0] or P2D[15:0]). I and Q data
arrive simultaneously and are sampled on the rising edge of an
internal sampling clock (SMP_CLK) that is synchronous with
DATACLK. In dual-port mode, driving the TXENABLE input
low powers down the digital datapath. TXENABLE should be
held high during normal data transmission.
INPUT DATA REFERENCED TO DATACLK
The simplest method of interfacing to the AD9785/AD9787/
AD9788 is when the input data is referenced to the DATACLK
output. The DATACLK output is phase-locked (with some
offset) to the internal clock that is used to latch the input data.
Therefore, if the setup and hold times of the input data with
respect to DATACLK are met, the interface timing latches in the
data correctly.
Table 25 shows the setup and hold time requirements for the
input data over the operating temperature range of the device.
Table 25 also shows the data valid window (DVW). The data
valid window is the sum of the setup and hold times of the
interface. This is the minimum amount of time valid data must
be presented to the device in order to ensure proper sampling.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSV | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80 |
| AD9786BSVRL | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP T/R |
| AD9786BSVZ | 功能描述:IC DAC 16BIT INTERPOL/SP 80TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC+® 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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