参数资料
型号: ADE5566ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 101/156页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: 770 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2V
电压 - 低输入/输出: 0.8V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
Data Sheet
Table 92. LCD Configuration X SFR (LCDCONX, Address 0x9C)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
7
6
[5:0]
Mnemonic
Reserved
EXTRES
BIASLVL
Default
0
0
0
Description
Reserved.
External resistor ladder selection bit.
EXTRES
Result
0
External resistor ladder is disabled. Charge pump is enabled
1
External resistor ladder is enabled. Charge pump is disabled
Bias level selection bits (see Table 93).
Table 93. LCD Bias Voltage When Contrast Control Is Enabled
1/2 Bias
1/3 Bias
BIASLVL [ 4:0 ]
V REF ×
? BIASLVL [ 4:0 ] ?
V REF × ? 1 + ?
BIASLVL[5]
0
1
V A (V)
31
? 31 ?
V B
V B = V A
V B = V A
V C
V C = 2 × V A
V C = 2 × V A
V B
V B = 2 × V A
V B = 2 × V A
V C
V C = 3 × V A
V C = 3 × V A
Table 9 4. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit
7
Mnemonic
AUTOSCREENSCROLL
Default
0
Description
When set, the four screens scroll automatically. The scrolling item is selected
by the BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96[5:4]). If both
BLINKEN in the LCD configuration SFR (LCDCON, Address 0x95[5]) and
AUTOSCREENSCROLL are set, this bit preempts the blinking mode.
6
INV_LVL
0
Frame inversion mode enable bit. If this bit is set, frames are inverted every other
frame. If this bit is cleared, frames are not inverted.
[5:4]
[3:2]
Reserved
SCREEN_SEL
00
00
These bits should be kept cleared to 0 for proper operation.
These bits select the screen that is being output on the LCD pins. Values of 0, 1, 2,
and 3 select Screen 0, Screen 1, Screen 2, and Screen 3, respectively.
1
UPDATEOVER
0
Update finished flag bit. This bit is updated by the LCD driver. When set, this bit
indicates that the LCD memory has been updated and a new frame has begun.
0
REFRESH
0
Refresh LCD data memory bit. This bit should be set by the user. When set, the
LCD driver does not use the data in the LCD data registers to update the display.
The LCD data registers can be updated by the 8052. When cleared, the LCD driver
uses the data in the LCD data registers to update the display at the next frame.
Table 9 5. LCD Clock SFR (LCDCLK, Address 0x96)
Bit
[7:6]
[5:4]
[3:0]
Mnemonic
BLKMOD
BLKFREQ
FD
Default
00
00
0000
Description
Blink mode clock source configuration bits.
BLKMOD
Result
00
The blink rate is controlled by software; the display is off
01
The blink rate is controlled by software; the display is on
10
The blink rate is 2 Hz
11
The blink rate is set by the BLKFREQ bits
Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD (Bits[7:6]) = 11.
BLKFREQ
Result (Blink Rate)
00
1 Hz
01
1/2 Hz
10
1/3 Hz
11
1/4 Hz
LCD frame rate selection bits (see Table 96 and Table 97).
Rev. D | Page 101 of 156
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