参数资料
型号: ADE5566ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 145/156页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: 770 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2V
电压 - 低输入/输出: 0.8V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
Data Sheet
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status
of the double-buffered receive and transmit registers. Figure
113 shows when the status and interrupt flags are raised. The
ADE5166/ADE5169/ADE5566/ADE5569
SFR, an overflow condition occurs. This overflow condition,
indicated by the SPIRxOF flag (SPISTAT[5]), forces the new data
to be discarded or overwritten, depending on the setting of the
RxOFW bit (SPIMOD1, Address 0xE8[2]).
transmit interrupt occurs when the transmit shift register is loaded
with the data in the SPI/I 2 C transmit buffer SFR (SPI2CTx, Address
0x9A). If the SPI master is in transmit operating mode and the
SPITx
SPITxIRQ = 1
TRANSMIT SHIFT REGISTER
SPIRx
SPIRxIRQ = 1
RECEIVE SHIFT REGISTER
SPI2CTx SFR has not been written with new data by the
beginning of the next byte transfer, the transmit operation
SPITx (EMPTY)
STOPS TRANSFER IF TIMODE = 1
SPIRx (FULL)
SPIRxOF = 1
stops.
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
When a new byte of data is received in the SPI/I 2 C receive buffer
SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt flag,
SPIRxIRQ (SPISTAT, Address 0xEA[4]), is raised. If the data in
the SPI/I 2 C receive buffer SFR (SPI2CRx, Address 0x9B) is not
read before new data is ready to be loaded into the SPI2CRx
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
Figure 113. SPI Receive and Transmit Interrupt and Status Flags
SPICPHA = 1
MISO
MOSI
SPIRx AND
SPITx FLAGS
WITH INTMOD = 1
SPIRx AND
SPITx FLAGS
WITH INTMOD = 0
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MISO
MOSI
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
?
SPICPHA = 0
SPIRx AND
SPITx FLAGS
WITH INTMOD = 1
SPIRx AND
SPITx FLAGS
WITH INTMOD = 0
Figure 114. SPI Timing Configurations
Rev. D | Page 145 of 156
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