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参数资料
| 型号： | ADE5566ASTZF62-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 143/156页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 输入阻抗： | 770 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2V |
| 电压 - 低输入/输出： | 0.8V |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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Data Sheet
Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
7
6
Mnemonic
BUSY
MMERR
Default
0
0
Description
SPI peripheral busy flag.
BUSY
Result
0
The SPI peripheral is idle.
1
The SPI peripheral is busy transferring data in slave or master mode.
SPI multimaster error flag. Write a 0 to this bit to clear it.
MMERR
Result
0
A multiple master error has not occurred.
1
If the SS_EN bit (SPIMOD1, Address 0xE8[3]) is set, enabling the slave select input and asserting
the SS pin while the SPI peripheral is transferring data as a master, this flag is raised to indicate
the error. Write a 0 to this bit to clear it.
5
SPIRxOF
0
SPI receive overflow error flag. Write a 0 to this bit to clear it.
SPIRxOF
TIMODE
Result
0
X 1
The SPI2CRx SFR (Address 0x9B) contains valid data.
1
1
Set if the SPI2CRx SFR is not read before the end of the next byte transfer. If the RxOFW
bit (SPIMOD1, Address 0xE8[2]) is set and this condition occurs, SPI2CRx is overwritten.
4
SPIRxIRQ
0
SPI receive mode interrupt flag. Write a 0 to this bit to clear it.
SPIRxIRQ
TIMODE
Result
0
X 1
The SPI2CRx SFR does not contain new data.
1
0
Set when the SPI2CRx SFR contains new data. If the SPI/I 2 C interrupt is enabled, an
interrupt is generated when this bit is set. If the SPI2CRx SFR is not read before the
end of the current byte transfer, the transfer stops and the SS pin is deasserted.
1
1
The SPI2CRx SFR contains new data.
3
2
SPIRxBF
SPITxUF
0
0
Status bit for the SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx SFR clears this flag.
Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx
(Address 0x9A). Write a 0 to this bit to clear it.
1
SPITxIRQ
0
SPI transmit mode interrupt flag. Write a 0 to this bit to clear it.
SPITxIRQ
TIMODE
Result
0
X 1
The SPI2CTx SFR is full.
1
0
The SPI2CTx SFR is empty.
1
1
Set when the SPI2CTx SFR is empty. If the SPI/I 2 C interrupt is enabled, an interrupt is
generated when this bit is set. If new data is not written to the SPI2CTx SFR before the
end of the current byte transfer, the transfer stops and the SS pin is deasserted.
0
SPITxBF
0
Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
1
X = don’t care.
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO (P0.5/MISO/ZX) pin is configured as an input line
in master mode and as an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte-wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (P0.4/MOSI/SDATA) pin is configured as an output
line in master mode and as an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte-
wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. The SCLK (P0.6/SCLK/T0) pin is configured as an
output in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
In slave mode, the SPIMOD2 SFR (Address 0xE9) must be con-
figured with the phase and polarity of the expected input clock.
In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPOL and SPICPHA bits (SPIMOD2[3:2])
be configured the same for the master and slave devices.
Rev. D | Page 143 of 156
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