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参数资料
型号： ADE5566ASTZF62-RL
厂商： Analog Devices Inc
文件页数： 11/156页
文件大小： 0K
描述： IC ENERGY METERING 1PHASE 64LQFP
产品变化通告： Product Discontinuance 27/Oct/2011
标准包装： 1,500
输入阻抗： 770 千欧
测量误差： 0.1%
电压 - 高输入/输出： 2V
电压 - 低输入/输出： 0.8V
电源电压： 2.4 V ~ 3.7 V
测量仪表类型： 单相
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 带卷 (TR)
Data Sheet
TIMING SPECIFICATIONS
AC inputs during testing were driven at V SWOUT ? 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at V IH
minimum for Logic 1 and at V IL maximum for Logic 0, as shown in
Figure 3.
ADE5166/ADE5169/ADE5566/ADE5569
For timing purposes, a port pin is no longer floating when
a 100 mV change from load voltage occurs. A port pin begins
to float when a 100 mV change from the loaded V OH /V OL level
occurs, as shown in Figure 3.
C LOAD = 80 pF for all outputs, unless otherwise noted. V DD = 2.7 V
to 3.6 V; all specifications T MIN to T MAX , unless otherwise noted.
V SWOUT – 0.5V
0.45V
0.2V SWOUT + 0.9V
TEST POINTS
0.2V SWOUT – 0.1V
V LOAD – 0.1V
V LOAD
V LOAD + 0.1V
TIMING
REFERENCE
POINTS
V LOAD – 0.1V
V LOAD
V LOAD – 0.1V
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameters
32.768 kHz External Crystal
Parameter
t CK
t CKL
t CKH
t CKR
t CKF
1/t CORE
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency 1
Min
Typ
30.52
6.26
6.26
9
9
1.024
Max
Unit
μs
μs
μs
ns
ns
MHz
1
The ADE5166/ADE5169/ADE5566/ADE5569 internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal
clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I 2 C-Compatible Interface Timing Parameters (400 kHz)
Parameter
t BUF
t L
t H
t SHD
t DSU
t DHD
t RSU
t PSU
t R
t F
t SUP 1
Description
Bus-free time between stop condition and start condition
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Rise time of both SCLK and SDATA
Fall time of both SCLK and SDATA
Pulse width of spike suppressed
Typ
1.3
1.36
1.14
251.35
740
400
12.5
400
200
300
50
Unit
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
1
Input filtering on both the SCLK and SDATA suppresses noise spikes of <50 ns.
t BUF
t SUP
t R
SDATA (I/O)
t PSU
t DSU
t SHD
MSB
t DHD
LSB
t H
t DSU
ACK
t RSU
t DHD
MSB
t F
t R
SCLK (I)
PS
1
2 TO 7
t L
8
t SUP
9
S(R)
t F
1
STOP
START
REPEATED
CONDITION CONDITION
Figure 4. I 2 C-Compatible Interface Timing
Rev. D | Page 11 of 156
START
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