参数资料
型号: ADE5566ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 51/156页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: 770 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2V
电压 - 低输入/输出: 0.8V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
Data Sheet
Voltage Channel ADC
Figure 48 shows the ADC and signal processing chain for the
voltage channel. In waveform sampling mode, the ADC outputs
a signed, twos complement, 24-bit data-word at a maximum
of 25.6 kSPS (MCLK/160). The ADC produces an output code
that is approximately between 0x28F5 (+10,485d) and 0xD70B
(?10,485d).
Channel Sampling
The waveform samples of the current ADC and voltage ADC
can also be routed to the waveform registers to be read by the
MCU core. The active, reactive, and apparent power and energy
calculation remain uninterrupted during waveform sampling.
ADE5166/ADE5169/ADE5566/ADE5569
When in waveform sampling mode, one of four output sample
rates can be chosen by using the two DTRT bits of the WAVMODE
register (Address 0x0D[1:0]), as shown in Table 35. The output
sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
If the WFSM enable bit is set in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB), the 8052 core has a pending ADE
interrupt. The sampled signals selected in the WAVMODE
register are latched into the waveform SFRs when the waveform
high byte (WAV1H or WAV2H) is read.
The ADE interrupt stays active until the WFSM status bit is
cleared (see the Energy Measurement Interrupts section).
×1, ×2, ×4,
×8, ×16
REFERENCE
ACTIVE AND REACTIVE
POWER CALCULATION
0.5V, 0.25V,
V2
V P
V N
V2
{GAIN[7:5]}
PGA2
ADC
HPF
VOLTAGE RMS (V rms )
CALCULATION
WAVEFORM SAMPLE
REGISTER
VOLTAGE PEAK DETECT
ZX DETECTION
0.125V, 62.5mV,
31.3mV
LPF1
0V
ANALOG
INPUT
RANGE
0x28F5
VOLTAGE CHANNEL
WAVEFORM
DATA RANGE
f –3dB = 63.7Hz
MODE1[6]
0x1DD0
0x0000
ZX SIGNAL
DATA RANGE FOR 60Hz SIGNAL
0x0000
0xE230
0xD70B
ZX SIGNAL
DATA RANGE FOR 50Hz SIGNAL
0x2037
0x0000
0xDFC9
Figure 48. ADC and Signal Processing in Voltage Channel
Rev. D | Page 51 of 156
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