参数资料
型号: ADE5566ASTZF62-RL
厂商: Analog Devices Inc
文件页数: 148/156页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: 770 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2V
电压 - 低输入/输出: 0.8V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
ADE5166/ADE5169/ADE5566/ADE5569
I 2 C RECEIVE AND TRANSMIT FIFOS
The I 2 C peripheral has a 4-byte receive FIFO and a 4-byte transmit
FIFO. The buffers reduce the overhead associated with using
the I 2 C peripheral. Figure 117 shows the operation of the I 2 C
receive and transmit FIFOs.
The Tx FIFO buffer can be loaded with four bytes to be transmitted
to the slave at the beginning of a write operation. When the trans-
mit FIFO is empty, the I 2 C transmit interrupt flag (I2CTxIRQ) is
Data Sheet
The Rx FIFO buffer allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can be
gener-ated after each byte is received or when the Rx FIFO is
full. If the peripheral is reading from a slave address, the communi-
cation stops when the number of received bytes equals the number
set in the I2CRCT bits in the I2CMOD SFR (Address 0xE8[4:0]).
An error, such as not receiving an acknowledgement, also causes
the communication to terminate.
CODE TO FILL Tx FIFO: CODE TO READ Rx FIFO:
set in the I 2 C interrupt status SFR (SPI2CSTAT, Address 0xEA[4]),
and the PC vectors to the I 2 C interrupt vector if this interrupt is
enabled. If a new byte is not loaded into the Tx FIFO before it is
needed in the transmit shift register, the communication stops.
MOV
MOV
MOV
MOV
I 2 CTx,
I 2 CTx,
I 2 CTx,
I 2 CTx,
TxDATA1
TxDATA2
TxDATA3
TxDATA4
I 2 CTx
MOV A,
MOV A,
MOV A,
MOV A,
I 2 CRx;
I 2 CRx;
I 2 CRx;
I 2 CRx;
RESULT: A = RxDATA1
RESULT: A = RxDATA2
RESULT: A = RxDATA3
RESULT: A = RxDATA4
I 2 CRx
An error, such as not receiving an acknowledgement, also causes
the communication to terminate. In case of an error during a
write operation, the Tx FIFO is flushed.
4-BYTE FIFO
TxDATA4
TxDATA3
TxDATA2
4-BYTE FIFO
RxDATA1
RxDATA2
RxDATA3
TxDATA1
TRANSMIT SHIFT REGISTER
RxDATA4
RECEIVE SHIFT REGISTER
Figure 117. I 2 C FIFO Operation
Rev. D | Page 148 of 156
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