参数资料
| 型号： | ADP3198JCPZ-RL |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/31页 |
| 文件大小： | 0K |
| 描述： | IC BUCK CTRLR 8BIT PROG 40LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VRM |
| 输入电压： | 12V |
| 输出数： | 4 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 带卷 (TR) |
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ADP3198
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-
OFF PROTECTION
The ADP3198 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During operation, the current
from ILIMIT is equal to 2/3 of IREF, giving 10 μA normally.
This current through the external resistor sets the ILIMIT
voltage, which is internally scaled to give a current limit
threshold of 82.6 mV/V. If the difference in voltage between
CSREF and CSCOMP rises above the current-limit threshold,
the internal current-limit amplifier controls the internal COMP
voltage to maintain the average output current at the limit.
If the limit is reached and TD5 in Figure 7 has completed, a
latch-off delay time starts, and the controller shuts down if the
fault is not removed. The current-limit delay time shares the
DELAY pin timing capacitor with the start-up sequence timing.
However, during current limit, the DELAY pin current is
reduced to IREF/4. A comparator monitors the DELAY voltage
and shuts off the controller when the voltage reaches 1.7 V.
Therefore, the current-limit latch-off delay time is set by the
current of IREF/4 charging the delay capacitor from 0 V to 1.7 V.
This delay is four times longer than the delay time during the
start-up sequence.
The current-limit delay time starts only after the TD5 is
complete. If there is a current limit during startup, the
ADP3198 goes through TD1 to TD5, and then starts the latch-
off time. Because the controller continues to cycle the phases
during the latch-off delay time, the controller returns to normal
operation and the DELAY capacitor is reset to GND if the short
is removed before the 1.7 V threshold is reached.
The latch-off function can be reset by either removing and
reapplying the supply voltage to the ADP3198, or by toggling
the EN pin low for a short time. To disable the short-circuit
latch-off function, an external resistor should be placed in
parallel with C DLY . This prevents the DELAY capacitor from
charging up to the 1.7 V threshold. The addition of this resistor
causes a slight increase in the delay times.
During startup, when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 1.5 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry. An inherent per-phase current limit protects
individual phases if one or more phases stop functioning
because of a faulty component. This limit is based on the
maximum normal mode COMP voltage. Typical overcurrent
latch-off waveforms are shown in Figure 9.
1
2
3
4
CH1 1V CH2 1V M 2ms A CH1 680mV
CH3 2V CH4 10V T 61.8%
Figure 9. Overcurrent Latch-Off Waveforms (Channel 1: CSREF,
Channel 2: DELAY, Channel 3: COMP, and Channel 4: Phase 1 Switch Node)
DYNAMIC VID
The ADP3198 has the ability to dynamically change the VID
inputs while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID on-
the-fly (OTF). A VID OTF can occur under light or heavy load
conditions. The processor signals the controller by changing the
VID inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.
When a VID input changes state, the ADP3198 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the eight
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and crowbar blanking functions for a
minimum of 100 μs to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level, when connected to a pull-up resistor, indicates that the
output voltage is within the nominal limits specified based on the
VID voltage setting. PWRGD goes low if the output voltage is
outside of this specified range, if the VID DAC inputs are in no
CPU mode, or if the EN pin is pulled low. PWRGD is blanked
during a VID OTF event for a period of 200 μs to prevent false
signals during the time the output is changing.
The PWRGD circuitry also incorporates an initial turn-on delay
time (TD5), based on the DELAY timer. Prior to the SS voltage
reaching the programmed VID DAC voltage and the PWRGD
masking-time finishing, the PWRGD pin is held low. Once the SS
pin is within 100 mV of the programmed DAC voltage, the
capacitor on the DELAY pin begins to charge. A comparator
monitors the DELAY voltage and enables PWRGD when the
voltage reaches 1.7 V. The PWRGD delay time is set, therefore, by
a current of IREF, charging a capacitor from 0 V to 1.7 V.
Rev. 2 | Page 13 of 31 | www.onsemi.com
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| ADP3199AJCPZ-RL | 功能描述:DC/DC 开关控制器 LSER SPEC VS ADP3193 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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