参数资料
| 型号： | ADP3198JCPZ-RL |
| 厂商： | ON Semiconductor |
| 文件页数： | 23/31页 |
| 文件大小： | 0K |
| 描述： | IC BUCK CTRLR 8BIT PROG 40LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VRM |
| 输入电压： | 12V |
| 输出数： | 4 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页
ADP3198
Equation 20 gives the designer a rough approximation for
determining the minimum ceramic capacitance. Due to the
complexity of the PCB parasitics and bulk capacitors, the actual
amount of ceramic capacitance required can vary.
This example uses 18, 10 μF 1206 MLC capacitors ( C Z = 180 μF).
The VID on-the-fly step change is 450 mV in 230 μs with a
settling error of 2.5 mV. The maximum allowable load release
overshoot for this example is 50 mV, therefore, solving for the
1 ? 1 ? 1 ? Δ I O ?
C Z ( MIN ) ≥
× ?
× ? ? D ? ?
?
?
320 nH × 100 A
C X ( MIN ) ≤ ?
? ? 4 × ? ? 1 . 0 mΩ +
? × 1 . 3 V
100 A ?
?
?
? ?
(20)
R O ? f SW ? n ? 2 S R ?
The typical ceramic capacitors consist of multiple 10 μF or
22 μF capacitors. For this example, Equation 20 yields 180.8 μF,
so eighteen, 10 μF ceramic capacitors suffice.
Next, there is an upper limit imposed on the total amount of
bulk capacitance yields
?
?
? ? 50 mV ?
?
?
?
?
? 180 μF ? = 3 . 92 mF
?
?
bulk capacitance (C X ) when the user considers the VID on-the-
fly voltage stepping of the output (voltage step V V in time t V
with error of V ERR ).
C X ( MAX ) ≤
320 nH × 450 mV
4 × 5 . 2 2 × ( 1 . 0 m Ω ) 2 × 1 . 3 V
×
? 230 μs × 1 . 3 V × 4 × 5 . 2 × 1 . 0 m Ω ?
?
?
? ? 1 ? ? 180 μF = 43.0 mF
? 1 + ?
?
A lower limit is based on meeting the capacitance for load
release for a given maximum load step (ΔI O ) and a maximum
allowable overshoot. The total amount of load release voltage
is given as Δ V O = Δ I O × R O + Δ V rl , where Δ V rl is the maximum
allowable overshoot voltage.
? 2 ?
? ?
?
? ? 450 mV × 320 nH ? ?
?
L × Δ I O
? n × ? ? R + Δ V rl ? ? × V
Δ I O ? ?
?
?
?
?
?
C X ( MIN ) ≥ ?
?
C X ( MAX ) ≤
? ? O VID
?
?
? C Z ?
?
?
(21)
(22)
where K = 5.2.
Using 10, 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ
each yields C X = 5.6 mF with an R X = 0.6 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (L X ) is low enough to limit the high frequency
ringing during a load change.
?
?
V V
?
× ? 1 + ? ? t V VID ×
×
nK R O
V VID
V V
?
?
where K = ? 1 n ? ? ERR
? .
? V V
?
?
?
? ? 1 ? ? C Z
?
L X ≤ 180 μF × ( 1 mΩ ) 2 ×
4
2 2
? V ?
?
?
L V
nKR O
L
2 ?
? ?
This is tested using
L X ≤ C Z × R O 2 × Q 2
(23)
= 24 0 pH
3
where Q 2 is limited to 4 / 3 to ensure a critically damped system.
To meet the conditions of these equations and transient
response, the ESR of the bulk capacitor bank (R X ) should be less
than two times the droop resistance (R O ). If the C X(MIN) is larger
than C X(MAX) , the system cannot meet the VID on-the-fly speci-
fication and can require the use of a smaller inductor or more
phases (and may have to increase the switching frequency to
keep the output ripple the same).
In this example, L X is approximately 240 pH for the 10, Al-Poly
capacitors, which satisfies this limitation. If the L X of the chosen
bulk capacitor bank is too large, the number of ceramic
capacitors needs to be increased, or lower ESL bulks need to be
used if there is excessive undershoot during a load transient.
For this multimode control technique, all ceramic designs can
be used providing the conditions of Equation 20 through
Equation 23 are satisfied.
Rev. 2 | Page 23 of 31 | www.onsemi.com
相关PDF资料 |
PDF描述 |
|---|---|
| ADP3207CJCPZ-RL | IC CTLR SYNC BUCK 7BIT 40-LFCSP |
| ADP3207DJCPZ-RL | IC CTLR BUCK 7BIT MULTI 40LFCSP |
| ADP3208CJCPZ-RL | IC CTLR BUCK 7BIT IMVP6 48LFCSP |
| ADP3208DJCPZ-RL | IC CTLR BUCK 7BIT 2PHASE 48LFCSP |
| ADP320ACPZ-110-R7 | IC REG LDO 3.3/3.3/1.5V 16LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP3199AJCPZ-RL | 功能描述:DC/DC 开关控制器 LSER SPEC VS ADP3193 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ADP3199JCPZ-RL | 功能描述:DC/DC 开关控制器 LSER SPEC VS ADP3193 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ADP32 | 功能描述:插座和适配器 EEROM-8U ADAPTER 32-PIN PLCC PACKAGE RoHS:否 制造商:Silicon Labs 产品:Adapter 用于:EM35x |
| ADP320 | 制造商:AD 制造商全称:Analog Devices 功能描述:Triple, 200 mA, Low Noise, High PSRR Voltage Regulator |
| ADP3203 | 制造商:AD 制造商全称:Analog Devices 功能描述:2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs |
发布紧急采购，3分钟左右您将得到回复。