参数资料
| 型号： | ADP3198JCPZ-RL |
| 厂商： | ON Semiconductor |
| 文件页数： | 24/31页 |
| 文件大小： | 0K |
| 描述： | IC BUCK CTRLR 8BIT PROG 40LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VRM |
| 输入电压： | 12V |
| 输出数： | 4 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 带卷 (TR) |
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ADP3198
P S ( MF ) = 2 × f SW × CC
× R G × MF × C ISS
n MF
n
POWER MOSFETS
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V GS(TH) , Q G , C ISS , C RSS , and R DS(ON) . The minimum gate drive
voltage (the supply voltage to the ADP3110A ) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V GATE ~10 V, logic-level threshold MOSFETs
(V GS(TH) < 2.5 V) are recommended.
The maximum output current (I O ) determines the R DS(ON)
requirement for the low-side (synchronous) MOSFETs. With
value for the switching loss per main MOSFET, where n MF is the
total number of main MOSFETs.
V × I O n
(25)
where R G is the total gate resistance (2 Ω for the ADP3110A and
about 1 Ω for typical high speed switching MOSFETs, making
R G = 3 Ω), and C ISS is the input capacitance of the main MOSFET.
Adding more main MOSFETs ( n MF ) does not help the switching
loss per MOSFET because the additional gate capacitance slows
switching. Use lower gate capacitance devices to reduce
switching loss.
? ? I
?
?
? n × I R
?
?
× ?
? +
= D × ? ? ? O
? × R DS ( MF )
P C ( MF )
12 ? ? n MF
? ? ? n MF
? ?
?
?
the ADP3198, currents are balanced between phases, thus, the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (n SF ). With conduction losses
being dominant, Equation 24 shows the total power that is
dissipated in each synchronous MOSFET in terms of the ripple
current per phase ( I R ) and average total output current ( I O ):
The conduction loss of the main MOSFET is given by the
following, where R DS(MF) is the on resistance of the MOSFET:
2 2
1
? ?
(26)
= ( 1 ? D ) × ? ? ? O
?
? +
?
× ? ?
?
?
? ?
P SF
? ? I
? ? ? n SF
?
2
1
12
? n I R
? n SF
?
?
2
?
? × R DS ( SF )
(24)
Typically, for main MOSFETs, the highest speed (low C ISS )
device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about
P DRV = ? SW × ( n MF × Q GMF + n SF × Q GSF ) + I CC ? × V CC (27)
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, the user can find the
required R DS(ON) for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50°C, a safe limit for P SF is 1 W to
1.5 W at 120°C junction temperature. Thus, for this example
(119 A maximum), R DS(SF) (per MOSFET) < 7.5 mΩ. This R DS(SF)
is also at a junction temperature of about 120°C. As a result,
users need to account for this when making this selection. This
example uses two lower-side MOSFETs at 4.8 mΩ, each at 120 ° C.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom-
mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3110A ). The output impedance of
the driver is approximately 2 Ω, and the typical MOSFET input
gate resistances are about 1 Ω to 2 Ω. Therefore, a total gate
capacitance of less than 6000 pF should be adhered to. Because
two MOSFETs are in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switching
speed on the rise and fall time of the gate driver impedance and
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
For this example, an NTD40N03L is selected as the main MOSFET
(eight total; nMF = 8), with CISS = 584 pF (maximum) and
RDS(MF) = 19 mΩ (maximum at TJ = 120°C). An NTD110N02L
is selected as the synchronous MOSFET (eight total; nSF = 8),
with CISS = 2710 pF (maximum) and RDS(SF) = 4.8 mΩ
(maximum at TJ = 120°C). The synchronous MOSFET CISS is
less than 3000 pF, satisfying this requirement.
Solving for the power dissipation per MOSFET at I O = 119 A and
I R = 11 A yields 958 mW for each synchronous MOSFET and
872 mW for each main MOSFET. A guideline to follow is to limit
the MOSFET power dissipation to 1 W. The values calculated in
Equation 25 and Equation 26 comply with this guideline.
Finally, consider the power dissipation in the driver for each
phase. This is best expressed as Q G for the MOSFETs and is
given by Equation 27, where Q GMF is the total gate charge for
each main MOSFET and Q GSF is the total gate charge for each
synchronous MOSFET.
? ?
? f ?
? 2 × n ?
Also shown is the standby dissipation factor (I CC × V CC ) of the
driver. For the ADP3110A , the maximum dissipation should be less
than 400 mW. In this example, with I CC = 7 mA, Q GMF = 5.8 nC,
and Q GSF = 48 nC, there is 297 mW in each driver, which is
below the 400 mW dissipation limit. See the ADP3110A data
sheet for more details.
MOSFET input capacitance, Equation 25 provides an approximate
Rev. 2 | Page 24 of 31 | www.onsemi.com
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