参数资料
| 型号： | ADP3198JCPZ-RL |
| 厂商： | ON Semiconductor |
| 文件页数： | 22/31页 |
| 文件大小： | 0K |
| 描述： | IC BUCK CTRLR 8BIT PROG 40LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VRM |
| 输入电压： | 12V |
| 输出数： | 4 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 带卷 (TR) |
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ADP3198
Load Line Setting
For load line values greater than 1 mΩ, R CSA can be set equal
By combining Equation 16 with Equation 14 and selecting
minimum values for the resistors, the following equations result:
to R O , and the LLSET pin can be directly connected to the
CSCOMP pin. When the load line value needs to be less than
R LL 2 =
I LIM × R O
50 μ A
(17)
R LL 1 = ? ? CSA ? 1 ? ? × R LL 2
1 mΩ, two additional resistors are required. Figure 12 shows
the placement of these resistors.
? R ?
? R O ?
(18)
ADP3198
Therefore, both R LL1 and R LL2 need to be in parallel and less than
CSCOMP
CSSUM
CSREF
18
17
16
8.33 kΩ.
Another useful feature for some VR applications is the ability to
select different load lines. Figure 12 shows an optional
MOSFET switch that allows this feature. Here, design for
R CSA = R O(MAX) (selected with Q LL on) and then use Equation 14
R LL 1
R LL 2
to set R O = R O(MIN) (selected with Q LL off).
LLSET
15
OPTIONAL LOAD LINE
SELECT SWITCH
Q LL
For this design, R CSA = R O = 1 mΩ. As a result, connect LLSET
directly to CSCOMP; the R LL1 and R LL2 resistors are not needed.
R O =
× R CSA
V VID ? V ONL
I FB
Figure 12. Load Line Setting Resistors
The two resistors R LL1 and R LL2 set up a divider between the
CSCOMP pin and CSREF pin. This resistor divider is input into
the LLSET pin to set the load line slope R O of the VR according
to the following equation:
R LL 2 (14)
R LL 1 + R LL 2
The resistor values for R LL1 and R LL2 are limited by two factors.
OUTPUT OFFSET
The Intel specification requires that at no load the nominal output
voltage of the regulator be offset to a value lower than the
nominal voltage corresponding to the VID code. The offset is
set by a constant current source flowing out of the FB pin (I FB ) and
flowing through R B . The value of R B can be found using
Equation 19.
R B =
?
The minimum value is based upon the loading of the
CSCOMP pin. This pin’s drive capability is 500 μA and the
R B =
1 . 3 V ? 1 . 285 V
15 μA
= 1 . 00 k Ω
(19)
majority of this should be allocated to the CSA feedback. If
the current through R LL1 and R LL2 is limited to 10% of this
The closest standard 1% resistor value is 1.00 kΩ.
I LIM × R CSA
50 × 10 ? 6
(50 μA), the following limit can be placed for the
minimum value for R LL1 and R LL2 :
R LL 1 + R LL 2 ≥
Here, I LIM is the current-limit current, which is the
maximum signal level that the CSA responds to.
(15)
C OUT SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Use some simple design guidelines to determine the require-
ments. These guidelines are based on having both bulk
capacitors and ceramic capacitors in the system.
R LL 1 × R LL 2 1 × 10 ? 3
120 × 10 ? 9
R LL 1 + R LL 2
?
The maximum value is based upon minimizing induced dc
offset errors based on the bias current of the LLSET pin. To
keep the induced dc error less than 1 mV, which makes this
error statistically negligible, place the following limit of the
parallel combination of R LL1 and R LL2 :
≤ = 8.33 kΩ (16)
First, select the total amount of ceramic capacitance. This is
based on the number and type of capacitor to be used. The best
location for ceramic capacitors is inside the socket with 12 to
18, 1206 size being the physical limit. Other capacitors can be
placed along the outer edge of the socket as well.
To determine the minimum amount of ceramic capacitance
required, start with a worst-case load step occurring right after
a switching cycle has stopped. The ceramic capacitance then
It is best to select the resistor values to minimize their values to
reduce the noise and parasitic susceptibility of the feedback path.
delivers the charge to the load while the load is ramping up and
until the VR has responded with the next switching cycle.
Rev. 2 | Page 22 of 31 | www.onsemi.com
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