参数资料
| 型号： | ADP3198JCPZ-RL |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/31页 |
| 文件大小： | 0K |
| 描述： | IC BUCK CTRLR 8BIT PROG 40LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VRM |
| 输入电压： | 12V |
| 输出数： | 4 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 带卷 (TR) |
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ADP3198
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 11 compliant
CPU application are as follows:
Assuming a desired TD2 time of 3 ms, C SS is 41 nF. The closest
standard value for C SS is 39 nF. Although C SS also controls the
C DLY = I DELAY ×
V DELAY ( TH )
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Input voltage (V IN ) = 12 V
VID setting voltage (V VID ) = 1.300 V
Duty cycle (D) = 0.108
Nominal output voltage at no load (V ONL ) = 1.285 V
Nominal output voltage at 115 A load (V OFL ) = 1.170 V
Static output voltage drop based on a 1.0 mΩ load line (R O )
from no load to full load (V D ) = V ONL ? V OFL =
1.285 V ? 1.170 V = 115 mV
Maximum output current (I O ) = 130 A
Maximum output current step (ΔI O ) = 100 A
Maximum output current slew rate (S R ) = 200 A/μs
Number of phases (n) = 4
Switching frequency per phase (f SW ) = 330 kHz
time delay for TD4 (determined by the final VID voltage), the
minimum specification for TD4 is 0 ns. This means that as long
as the TD2 time requirement is met, TD4 is within the
specification.
CURRENT-LIMIT LATCH-OFF DELAY TIMES
The start-up and current-limit delay times are determined by
the capacitor connected to the DELAY pin. The first step is to
set C DLY for the TD1, TD3, and TD5 delay times (see Figure 7).
The DELAY ramp ( I DELAY ) is generated using a 15 μA internal
current source. The value for C DLY can be approximated using
TD ( x )
(3)
where TD(x) is the desired delay time for TD1, TD3, and TD5.
The DELAY threshold voltage ( V DELAY(TH) ) is given as 1.7 V. In
this example, 2 ms is chosen for all three delay times, which
SETTING THE CLOCK FREQUENCY
The ADP3198 uses a fixed frequency control architecture. The
frequency is set by an external timing resistor (R T ). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
as well as the sizes of the inductors, the input capacitors, and
output capacitors. With n = 4 for four phases, a clock frequency
of 1.32 MHz sets the switching frequency (f SW ) of each phase to
330 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Figure 6 shows that to achieve a 1.32 MHz oscillator frequency,
the correct value for R T is 130 kΩ. Alternatively, the value for R T
can be calculated using
meets Intel specifications. Solving for C DLY gives a value of
17.6 nF. The closest standard value for C DLY is 18 nF.
When the ADP3198 enters current limit, the internal current
source changes from 15 μA to 3.75 μA. This makes the latch-off
delay time four times longer than the start-up delay time.
Longer latch-off delay times can be achieved by placing a
resistor in parallel with C DLY .
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs. However, using smaller inductors
R T =
1
n × f SW × 6 pF
(1)
allows the converter to meet a specified peak-to-peak transient
deviation with less total output capacitance. Conversely, a higher
inductance means lower ripple current and reduced conduction
C SS = 15 μ A ×
V BOOT
V VID × ( 1 ? D )
f SW × L
where 6 pF is the internal IC component values. For good initial
accuracy and frequency stability, a 1% resistor is recommended.
SOFT START DELAY TIME
The value of C SS sets the soft start time. The ramp is generated
with a 15 μA internal current source. The value for C SS can be
found using
TD 2
(2)
losses, but more output capacitance is required to meet the
same peak-to-peak transient deviation.
In any multiphase converter, a practical value for the peak-to-
peak inductor ripple current is less than 50% of the maximum
dc current in the same inductor. Equation 4 shows the
relationship between the inductance, oscillator frequency, and
peak-to-peak ripple current in the inductor.
I R = (4)
where TD2 is the desired soft start time, and V BOOT is internally
set to 1.1 V.
Rev. 2 | Page 19 of 31 | www.onsemi.com
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