参数资料
| 型号： | ADP3198JCPZ-RL |
| 厂商： | ON Semiconductor |
| 文件页数： | 25/31页 |
| 文件大小： | 0K |
| 描述： | IC BUCK CTRLR 8BIT PROG 40LFCSP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VRM |
| 输入电压： | 12V |
| 输出数： | 4 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 带卷 (TR) |
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ADP3198
RAMP RESISTOR SELECTION
The ramp resistor (R R ) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the best
combination of thermal balance, stability, and transient response.
Equation 28 is used for determining the optimum value.
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor value
for R LIM . The current-limit threshold for the ADP3198 is set
with a constant current source flowing out of the ILIMIT pin,
which sets up a voltage (V LIM ) across R LIM with a gain of
= LIM
V CL I × R CSA
A LIM × I ILIMIT
R R =
R R =
A R × L
3 × A D × R DS × C R
0.2 × 320 nH
3 × 5 × 2.4 m Ω × 5 pF
= 356 kΩ
(28)
82.6 mV/V (A LIM ). Thus, increasing R LIM now increases the
current limit. R LIM can be found using
R LIM = × R REF (31)
82 . 6 mV
Here, I LIM is the peak average current limit for the supply output.
A R × ( 1 ? D ) × V VID
R R × C R × f SW
V R = = 39 4 m V
V COMP ( MAX ) ? V BIAS
V RT
D MAX ( V IN ? V VID )
f SW
I PHMAX ? × (33)
V COMP ( CLAMPED ) ? V BIAS
A D × R DS ( MAX )
where:
A R is the internal ramp amplifier gain.
A D is the current balancing amplifier gain.
R DS is the total low-side MOSFET on resistance.
C R is the internal ramp capacitor value.
The internal ramp voltage magnitude can be calculated by using
V R =
(29)
0.2 × ( 1 ? 0.108 ) × 1.3 V
357 k Ω × 5 pF × 330 kHz
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and noise rejection improves, but
transient degrades. Likewise, if the ramp is made smaller,
transient response improves at the sacrifice of noise rejection
and stability.
The factor of 3 in the denominator of Equation 28 sets a ramp
size that gives an optimal balance for good stability, transient
response, and thermal balance.
COMP PIN RAMP
A ramp signal on the COMP pin is due to the droop voltage
and output voltage ramps. This ramp amplitude adds to the
internal ramp to produce the following overall ramp signal
at the PWM input:
The peak average current is the dc current limit plus the output
ripple current. In this example, choosing a dc current limit of
159 A and having a ripple current of 11 A gives an I LIM of 170 A.
This results in an R LIM = 205.8 kΩ, for which 205 kΩ is chosen
as the nearest 1% value.
The per-phase initial duty cycle limit and peak current during a
load step are determined by
D MAX = D × (32)
L
For the ADP3198, the maximum COMP voltage (V COMP(MAX) )
is 4.0 V and the COMP pin bias voltage (V BIAS ) is 1.1 V. In this
example, the maximum duty cycle is 0.61 and the peak current
is 62 A.
The limit of the peak per-phase current described earlier during
the secondary current limit is determined by
I PHLIM ? (34)
For the ADP3198, the current balancing amplifier gain (A D ) is 5
and the clamped COMP pin voltage is 2 V. Using an R DS(MAX) of
2.8 mΩ (low-side on resistance at 150°C) results in a per-phase
peak current limit of 64 A. This current level can be reached only
with an absolute short at the output, and the current-limit latch-off
function shuts down the regulator before overheating can occur.
FEEDBACK LOOP COMPENSATION DESIGN
? 1 ?
?
?
?
V RT =
?
?
V R
2 × ( 1 ? n × D )
n × f SW × C X × R O
?
?
(30)
Optimized compensation of the ADP3198 allows the best
possible response of the regulator output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
In this example, the overall ramp signal is 0.46 V. However,
if the ramp size is smaller than 0.5 V, increase the ramp size
to be at least 0.5 V by decreasing the ramp resistor for noise
immunity. Because there is only 0.46 V initially, a ramp resistor
value of 332 kΩ is chosen for this example, yielding an overall
ramp of 0.51 V.
that is entirely resistive over the widest possible frequency
range, including dc, and equal to the droop resistance (R O ).
With the resistive output impedance, the output voltage droops
in proportion to the load current at any load current slew rate.
This ensures optimal positioning and minimizes the output
decoupling.
Rev. 2 | Page 25 of 31 | www.onsemi.com
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相关代理商/技术参数 |
参数描述 |
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| ADP3199AJCPZ-RL | 功能描述:DC/DC 开关控制器 LSER SPEC VS ADP3193 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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