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| 型号： | ADSP-21161NCCAZ100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/60页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 225MBGA |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 100MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 225-BGA，CSPBGA |
| 供应商设备封装： | 225-CSPBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | ADSP21161NCCAZ100 |
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Rev. C
|
Page 12 of 60
|
January 2013
BRST
I/O/T
Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data associated with consecutive
addresses is being read or written. A slave device samples the initial address and increments an internal
address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-
21161N in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol.
BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for
the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the DSP’s
BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N
with ID2–0 =00x.
ACK
I/O/S
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21161N deasserts ACK as an output to add wait states to a synchronous
access of its IOP registers. ACK has a 20 k
internal pull-up resistor that is enabled during reset or on DSPs
with ID2–0 =00x.
SBTS
I/S
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161N attempts to
access external memory while SBTS is asserted, the processor will halt and the memory access will not be
completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21161N
deadlock.
CAS
I/O/T
SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
RAS
I/O/T
SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines
the operation for the SDRAM to perform.
SDWE
I/O/T
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the
operation for the SDRAM to perform.
DQM
O/T
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command
and during SDRAM power-up initialization.
SDCLK0
I/O/S/T
SDRAM Clock Output 0. Clock for SDRAM devices.
SDCLK1
O/S/T
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices,
handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or
both SDCLKx pins can be three-stated.
SDCKE
I/O/T
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with the
SDRAM device.
SDA10
O/T
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host
accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
IRQ2–0
I/A
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered
or level-sensitive.
FLAG11–0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a
condition. As an output, it can be used to signal external peripherals.
TIMEXP
O
Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to
zero.
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161N’s external
bus. When HBR is asserted in a multiprocessing system, the ADSP-21161N that is bus master will relinquish
the bus and assert HBG. To relinquish the bus, the ADSP-21161N places the address, data, select, and strobe
lines in a high impedance state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multipro-
cessing system.
HBG
I/O
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of
the external bus. HBG is asserted (held low) by the ADSP-21161N until HBR is released. In a multiprocessing
system, HBG is output by the ADSP-21161N bus master and is monitored by all others.
After HBR is asserted, and before HBG is given, HBG will float for 1 tCK (1 CLKIN cycle). To avoid erroneous
grants, HBG should be pulled up with a 20 k
to 50 k external resistor.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-21161N.
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
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| ADSP-21161NKCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21261 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Embedded Processor |
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