参数资料
型号: ADSP-BF535PBBZ-200
厂商: Analog Devices Inc
文件页数: 11/44页
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 260-BGA
产品培训模块: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
标准包装: 1
系列: Blackfin®
类型: 定点
接口: PCI,SPI,SSP,UART,USB
时钟速率: 200MHz
非易失内存: 外部
芯片上RAM: 308kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.50V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 260-BBGA
供应商设备封装: 260-PBGA(19x19)
包装: 托盘
–19–
REV. A
ADSP-BF535
TRST
IJTAG reset.
RESET
I
When this pin is asserted to logic zero level for at least 10 CLKIN cycles, a hardware reset
is initiated. The minimum pulse width for power-on reset is 40 s.
CLKIN1
I
Clock in.
BYPASS
I
Dedicated mode pin. May be permanently strapped to VDD or VSS. Bypasses the on-chip
PLL.
DEEPSLEEP
O
Denotes that the Blackfin processor core is in Deep Sleep mode.
BMODE2 – 0
I
Dedicated mode pin. May be permanently strapped to VDD or VSS. Configures the boot
mode that is employed following hardware reset or software reset.
PCI_AD31 –0
I/O/T PCI address and data bus.
PCI_CBE3–0
I/O/T PCI byte enables.
PCI_FRAME
I/O/T PCI frame signal. Used by PCI initiators for signalling the beginning and end of a PCI
transaction.
PCI_IRDY
I/O/T PCI initiator ready signal.
PCI_TRDY
I/O/T PCI target ready signal.
PCI_DEVSEL
I/O/T PCI device select signal. Asserted by targets of PCI transactions to claim the transaction.
PCI_STOP
I/O/T PCI stop signal.
PCI_PERR
I/O/T PCI parity error signal.
PCI_PAR
I/O/T PCI parity signal.
PCI_REQ
O
PCI request signal. Used for requesting the use of the PCI bus.
PCI_SERR
I/O/T PCI system error signal. Requires a pull-up on the system board.
PCI_RST
I/O/T PCI reset signal.
PCI_GNT
I
PCI grant signal. Used for granting access to the PCI bus.
PCI_IDSEL
I
PCI initialization device select signal. Individual device selects for targets of PCI config-
uration transactions.
PCI_LOCK
I
PCI lock signal. Used to lock a target or the entire PCI bus for use by the master that
asserts the lock.
PCI_CLK
I
PCI clock.
PCI_INTA
I/O/T PCI interrupt A line on PCI bus. Asserted by the ADSP-BF535 Blackfin processor as a
device-to-signal an interrupt to the system processor. Monitored by the ADSP-BF535
when acting as the system processor.
PCI_INTB
I
PCI interrupt B line. Monitored by ADSP-BF535 Blackfin processor when acting as the
system processor.
PCI_INTC
I
PCI interrupt C line. Monitored by the ADSP-BF535 Blackfin processor when acting as
the system processor.
PCI_INTD
I
PCI interrupt D line. Monitored by the ADSP-BF535 Blackfin processor when acting as
the system processor.
XTAL1
I
Real-Time Clock oscillator input.
XTAL0
O
Real-Time Clock oscillator output.
EMU
O
Emulator acknowledge, open drain. Must be connected to the ADSP-BF535 Blackfin
processor emulator target board connector only.
VDDPLL
P
PLL power supply (1.5 V nominal).
VDDRTC
P
Real-Time Clock power supply (3.3 V nominal).
VDDEXT
P
I/O (except PCI) power supply (3.3 V nominal).
VDDPCIEXT
P
PCI I/O power supply (3.3 V nominal).
VDDINT
P
Internal power supply (1.5 V nominal).
GND
G
Power supply return.
Table 7. Pin Descriptions (continued)
Pin
Type
Function
Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state
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