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| 型号： | ADSP-BF535PBBZ-200 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/44页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 260-BGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | PCI，SPI，SSP，UART，USB |
| 时钟速率： | 200MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 308kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.50V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 260-BBGA |
| 供应商设备封装： | 260-PBGA（19x19） |
| 包装： | 托盘 |
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ADSP-BF535
–6–
REV. A
Booting
The ADSP-BF535 Blackfin processor contains a small boot
kernel, which configures the appropriate peripheral for booting.
If the ADSP-BF535 Blackfin processor is configured to boot from
boot ROM memory space, the processor starts executing from
the on-chip boot ROM. For more information, see Booting
Event Handling
The event controller on the ADSP-BF535 Blackfin processor
handles all asynchronous and synchronous events to the proces-
sor. The ADSP-BF535 Blackfin processor provides event
handling that supports both nesting and prioritization. Nesting
allows multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher-priority event
takes precedence over servicing of a lower priority event. The
controller provides support for five different types of events:
Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
Reset—This event resets the processor.
Non-Maskable Interrupt (NMI)—The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly
shutdown of the system.
Exceptions—Events that occur synchronously to program
flow, for example, the exception will be taken before the
instruction is allowed to complete. Conditions such as
data alignment violations, undefined instructions, and so
on, cause exceptions.
Interrupts—Events that occur asynchronously to
program flow. They are caused by timers, peripherals,
input pins, explicit software instructions, and so on.
Each event has an associated register to hold the return address
and an associated return-from-event instruction. The state of the
processor is saved on the supervisor stack, when an event is
triggered.
The ADSP-BF535 Blackfin processor event controller consists
of two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF535 Blackfin processor.
Table 1 describes the inputs to the CEC, identifies their names
in the Event Vector Table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF535 Blackfin processor provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the
Interrupt Assignment Registers (IAR). Table 2 describes the
inputs into the SIC and the default mappings into the CEC.
Table 1. Core Event Controller (CEC)
Priority
(0 is Highest)
Event Class
EVT Entry
0Emulation/Test
EMU
1
Reset
RST
2
Non-Maskable
NMI
3
Exceptions
EVX
4
Global Enable
5Hardware Error
IVHW
6Core Timer
IVTMR
7
General Interrupt 7
IVG7
8
General Interrupt 8
IVG8
9
General Interrupt 9
IVG9
10
General Interrupt 10
IVG10
11
General Interrupt 11
IVG11
12
General Interrupt 12
IVG12
13
General Interrupt 13
IVG13
14
General Interrupt 14
IVG14
15
General Interrupt 15
IVG15
Table 2. System Interrupt Controller (SIC)
Peripheral Interrupt
Event
Peripheral
Interrupt ID
Default
Mapping
Real-Time Clock
0
IVG7
Reserved
1
USB
2
IVG7
PCI Interrupt
3
IVG7
SPORT 0 Rx DMA
4
IVG8
SPORT 0 Tx DMA
5
IVG8
SPORT 1 Rx DMA
6
IVG8
SPORT 1 Tx DMA
7
IVG8
SPI 0 DMA
8
IVG9
SPI 1 DMA
9
IVG9
UART 0 Rx
10
IVG10
UART 0 Tx
11
IVG10
UART 1 Rx
12
IVG10
UART 1 Tx
13
IVG10
Timer 0
14
IVG11
Timer 1
15
IVG11
Timer 2
16
IVG11
GPIO Interrupt A
17
IVG12
GPIO Interrupt B
18
IVG12
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