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型号： ADSP-BF535PBBZ-200
厂商： Analog Devices Inc
文件页数： 30/44页
文件大小： 0K
描述： IC DSP CONTROLLER 16BIT 260-BGA
产品培训模块： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
标准包装： 1
系列： Blackfin®
类型： 定点
接口： PCI，SPI，SSP，UART，USB
时钟速率： 200MHz
非易失内存： 外部
芯片上RAM： 308kB
电压 - 输入/输出： 3.30V
电压 - 核心： 1.50V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 260-BBGA
供应商设备封装： 260-PBGA（19x19）
包装： 托盘
ADSP-BF535
–36–
REV. A
Output Drive Currents
Figure 19 through Figure 21 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF535 Blackfin
processor. The curves represent the current drive capability of
the output drivers as a function of output voltage. Figure 19
applies to the
ABE3–0, SDQM3–0, ADDR25–2, AMS3–0,
AOE, ARE, AWE, CLKOUT, SCLK1, DATA31–0, DT1–0,
EMU, MISO1–0, MOSI1–0, PF15–0, RFS1–0, RSCLK1–0,
SA10,
SCAS, SCK1–0, SCKE, SCLK0, DEEPSLEEP,
SMS3–0, SRAS, SUSPEND, SWE, TDO, TFS1–0, TMR2–0,
TSCLK1–0, TX1–0, TXDMNS, TXDPLS,
TXEN, and
XTAL0 pins. Figure 20 applies to the PCI_AD31–0,
PCI_CBE3–0, PCI_DEVSEL, PCI_FRAME, PCI_INTA,
PCI_IRDY, PCI_PAR, PCI_PERR, PCI_RST, PCI_SERR,
PCI_STOP, and PCI_TRDY pins. Figure 21 applies to the
PCI_REQ pin.
Power Dissipation
Total power dissipation has two components: one due to internal
circuitry (PINT) and one due to the switching of external output
drivers (P
EXT). Table 26 shows the power dissipation for internal
circuitry (VDDINT). Internal power dissipation is dependent on the
instruction execution sequence and the data operands involved.
Table 27 shows the power dissipation for the phase-locked loop
(PLL) circuitry (VDDPLL).
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Maximum frequency (f0) at which all output pins can
switch during each cycle
Their load capacitance (C0) of all switching pins
Their voltage swing (V
DDEXT)
The external component is calculated using:
Figure 19. Output Drive Current
Figure 20. PCI 33 MHz Output Drive Current
200
150
100
50
0
100
150
200
50
VOH (VDDEXT = 3.45V, 40°C)
VOH (VDDEXT =3.45V, 0°C)
VOH (VDDEXT = 3.15V, +105°C)
VOH (VDDEXT = 2.5V, +85°C)
VOH (VDDEXT = 3.3V, +25°C)
VOL (VDDEXT = 3.3V, +25°C)
VOL (VDDEXT = 2.5V, +85°C)
VOL (VDDEXT =3.45V, 0°C)
VOL (VDDEXT = 3.15V, +105°C)
VOL (VDDEXT =3.45V, 40°C)
SOURCE (VO) VOLTAGE – V
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
S
O
U
R
C
E
(I
O
)
C
U
R
E
N
T
–
m
A
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
200
150
100
50
0
50
100
150
VOH (VDDEXT =3.3V, +25°C)
VOH (VDDEXT =2.5V,
+85°C)
VOH (VDDEXT =3.45V, 0°C)
VOH (VDDEXT = 3.15V, +105°C)
VOH (VDDEXT = 3.45V, 45°C)
VOL (VDDEXT = 3.3V, +25°C)
VOL (VDDEXT =2.5V, +85°C)
VOL (VDDEXT =3.45V,0°C)
VOL (VDDEXT = 3.15V, +105°C)
VOL (VDDEXT =3.45V, 45°C)
S
O
U
R
C
E
(I
O
)
C
U
R
E
N
T
–
m
A
SOURCE (VO) VOLTAGE – V
200
250
300
Figure 21. PCI_REQ Output Drive Current
Table 26. Internal Power Dissipation
Test Conditions
1
1 IDD data is specified for typical process parameters. All data at 25C.
Parameter
fCCLK =
100 MHz
VDDINT =
1.0 V
fCCLK =
200 MHz
VDDINT =
1.2 V
fCCLK =
300 MHz
VDDINT =
1.5 V
fCCLK =
350 MHz
VDDINT =
1.6 V
Unit
IDDTYP
2
2 Processor executing 75% dual Mac, 25% ADD with moderate data bus
activity.
96.0
206.0
387.0
498.0
mA
IDDEFR
3
3 Implementation of Enhanced Full Rate (EFR) GSM algorithm.
114.0
248.0
463.0
579.0
mA
IDDSLEEP
4
4 See the ADSP-BF535 Blackfin Processor Hardware Reference Manual for
definitions of Sleep and Deep Sleep operating modes.
15.0
29.0
52.0
62.0
mA
IDDDEEPSLEEP
4 4.0
5.0
8.2
9.8
mA
IDDRESET
5
5IDD is specified for when the device is in the reset state.
132.0
255.0
485.3
651.0
mA
SOURCE (VO) VOLTAGE – V
S
O
U
R
C
E
(I
O
)
C
U
R
E
N
T
–
m
A
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
4.0
200
150
100
50
0
50
100
150
200
VOH (VDDEXT =3.3V, +25°C)
VOH (VDDEXT = 2.5V, +85°C)
VOH (VDDEXT = 3.45V, 0°C)
VOH (VDDEXT = 3.15V,
+105°C)
VOH (VDDEXT =3.45V, 45°C)
VOL (VDDEXT = 3.3V, +25°C)
VOL (VDDEXT =2.5V, +85°C)
VOL (VDDEXT = 3.45V, 0°C)
VOL (VDDEXT = 3.15V, +105°C)
VOL (VDDEXT =3.45V, 45°C)
PEXT
VDDEXT
2
C
0
f
0
×
∑
×
=
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