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参数资料
| 型号： | CS4103VHG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | IEEE P1394a Physical Layer Device |
| 中文描述： | 3 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | LQFP-80 |
| 文件页数： | 15/24页 |
| 文件大小： | 423K |
| 代理商： | CS4103VHG |
Revision 1.0
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G
Register Descriptions
(Continued)
Address 04h
0
Link_active
R/W
1
Link Active:
The logical AND of Link_active and LPS active sets the L bit of
the nodes self-ID packet.
Contender:
Cleared or set by software to control the value of the C (Con-
tender) bit transmitted in self-ID packet zero.
Jitter:
The difference between the fastest and slowest repeater delay,
expressed as (jitter + 1) * 20ns.
Power Class:
Controls the value of the pwr field transmitted in the self_ID
packet. Upon reset, the value of the PC[0:2] strapping pins is loaded into this
field. This field may be subsequently written by software. Power Class is
application dependent (see P1394a specification, Table 8-3).
*Reset value is application dependent.
1
Contender
R/W
0
2:4
Jitter
R
000
5:7
Pwr_class
R/W
*
Address 05h
0
Resume_int
RW
0
Resume Interrupt Enable:
When set to one, the CS4103 sets Port_event to
one if resume operations commence for any port.
Initiate short (arbitrated) Bus Reset:
When set, an arbitrated short bus
reset will be issued by the CS4103. This bit is self-clearing.
Loop Detect:
Indicates a loop in the cable topology. A write of one to this bit
clears it to zero. A software clear of this bit will occur if a cable loop is
present.
Cable Power Failure Detect:
Set to one when the PS bit changes from one
to zero. A write of one to this bit clears it to zero.
Arbitration State Machine Timeout:
A write of one to this bit clears it to
zero.
Port Event Detect:
The CS4103 sets this bit to one if any of Connected,
Bias, Disabled or Fault change for a port whose Int_Enable bit is one. The
CS4103 also sets this bit to one if resume operations commence for any port
and Resume_int is one. A write of one to this bit clears it to zero.
Enable Arbitration Acceleration:
When set, the CS4103 uses the
enhancements specified in clause 7.10. CS4103 behavior is unspecified if
the value of Enab_accel is changed while a bus request is pending.
Enable Multi-speed Packet Concatenation:
When set, the link signals the
speed of all packets to the CS4103.
1
ISBR
RW
0
2
Loop
RW
0
3
Pwr_fail
RW
0
4
Timeout
RW
0
5
Port_event
RW
0
6
Enab_accel
RW
0
7
Enab_multi
RW
0
Address 06h
0:7
RSVD
--
--
Reserved
Address 07h
0:2
Page_select
RW
000
Page Select:
Selects one of eight register pages of which only pages 0, 1,
and 7 are defined. The selected page is accessible at Addresses 08h
through 0Fh.
Reserved
Port Select:
Selects per port information of a register page. If a register
page has per port registers this field selects which port registers are accessi-
ble at Addresses 08h through 0Fh.
3
RSVD
Port_select
--
--
4:7
RW
0000
Table 3-5. Base Registers (Continued)
Bit
Name
Access
Reset
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