参数资料
型号: CS4103VHG
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 微控制器/微处理器
英文描述: IEEE P1394a Physical Layer Device
中文描述: 3 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP80
封装: LQFP-80
文件页数: 18/24页
文件大小: 423K
代理商: CS4103VHG
www.national.com
18
Revision 1.0
G
Register Descriptions
(Continued)
3.5
The Vendor Specific page is reserved for vendor use. It
may contain per-port registers but this implementation
does not require port selection to access user defined reg-
VENDOR SPECIFIC: PAGE 7, PORTS[0:2]
isters. The Vendor Specific page is accessible by setting
the Page_select field in the Base register at Address 07h to
0111b.
Table 3-10. Vendor Specific: Page 7 Bit Map
Address
0
1
2
3
4
5
6
7
08h-0Eh
0Fh
RSVD
RSVD
PD[0]
PD[1]
RSVD
Table 3-11. Vendor Specific: Page 7 Registers
Bits
Name
Access
Reset
Description
Addresses 08h-0Eh
Page 7, Port[n], Register-0 through Register-6
0:7
RSVD
RW
00h
Reserved:
Do not set bits in these fields. Setting bits in these fields may
cause noncompliant or unspecified behavior.
Addresses 0Fh
Page 7, Port[n], Register-7
0:2
RSVD
RW
00h
Reserved:
Do not set bits in these fields. Setting bits in these fields may
cause noncompliant or unspecified behavior.
Power Down Mode:
The CS4103 will transition to a low power state defined
by these bits when the PHY-Link interface is disabled and the PHY ports are
in the disabled, disconnected or suspended state.
00 = No Power Down.
01 = Stop PLL and 50 MHz clock.
10 = Stop 50 MHz clock.
11 = Stop Crystal, PLL, and 50 MHz clock.
Reserved:
Do not set bits in these fields. Setting bits in these fields may
cause noncompliant or unspecified behavior.
3:4
PD[1:0]
RW
00
5:7
RSVD
RW
00h
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