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参数资料
| 型号： | CS4103VHG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | IEEE P1394a Physical Layer Device |
| 中文描述： | 3 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封装： | LQFP-80 |
| 文件页数： | 5/24页 |
| 文件大小： | 423K |
| 代理商： | CS4103VHG |
Revision 1.0
5
www.national.com
G
2.0
This section defines the signals and external interface of
the CS4103. Figure 2-1 shows the pins organized by their
functional groupings (internal test and electrical pins are
not shown).
Signal Definitions
2.1
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
PIN ASSIGNMENT
Figure 2-2 on page 6 shows the pin assignment for the
CS4103 with Tables 2-2 and 2-3, on pages 7 and 8, listing
the pin assignments sorted by pin number and alphabeti-
cally by signal name.
Section 2.2 "Signal Descriptions" starting on page 9 pro-
vides a description for each signal within its associated
functional group.
Figure 2-1. Signal Groups
Table 2-1. Pin Type Definitions
Mnemonic
Definition
I
Input Pin
I/O
Bidirectional Pin
O
Output
t/s
TRI-STATE Signal
VDD
2.5V Core Power Supply
VDDIO
3.3V I/O Power Supply
VSS
Ground Connection
TPA[0:2]+
TPA[0:2]–
TBA[0:2]+
TPB[0:2]–
TPBIAS[0:2]
DATA[0:7]
CTRL[0:1]
LREQ
SCLK
LPS
LNKON
LOCKIND
PHY-Link
Interface
Geode
CS4103
Transceiver/
1394 Cable
Connections
DIRECT
XI
XO
RESET#
Clock/Crystal
and
Reset
Connection
PC0
PC1
PC2
Power to/from
Bus
CPS
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