参数资料
型号: CS80C286-16
厂商: Intersil
文件页数: 23/60页
文件大小: 0K
描述: IC CPU 16BIT 5V 16MHZ 68-PLCC
标准包装: 126
处理器类型: 80C286 16-位
速度: 16MHz
电压: 5V
安装类型: 表面贴装
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24.23x24.23)
包装: 管件
3
68 LEAD PLCC
P.C. Board View - As viewed from the component side of the P.C. board.
Functional Diagram
Pinouts (Continued)
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
VSS
BHE
NC
S1
S0
PEACK
A23
A22
VSS
A21
A20
A19
A18
A17
A16
A15
A14
LOCK
M/
IO
COD
/INTA
HLDA
HOLD
RE
ADY
V
CC
PE
RE
Q
V
SS
NMI
NC
IN
T
R
NC
BUS
Y
ER
ROR
NC
A1
3
A1
2
A11
A1
0
A9
A8
A7
A6
A5
A4
A3
R
ESE
T
V
CC
CLK
A2
A1
A0
PIN 1 INDICATOR
MOLD MARK DOES NOT
INDICATE PIN 1
OFFSET
ADDER
SEGMENT
LIMIT
CHECKER
SEGMENT
BASES
SEGMENT
SIZES
PHYSICAL
ADDRESS
ADDER
ALU
CONTROL
REGISTERS
ADDRESS
LATCHES AND DRIVERS
PRE-
BUS CONTROL
FETCHER
PROCESSOR
EXTENSION
INTERFACE
DATA TRANSCEIVERS
6-BYTE
PREFETCH
QUEUE
INSTRUCTION
UNIT (IU)
BUS UNIT (BU)
EXECUTION UNIT (EU)
ADDRESS UNIT (AU)
A23 - A0,
BHE, M/IO
PEACK
3 DECODED
INSTRUCTION
QUEUE
INSTRUCTION
DECODER
PEREQ
READY,
HOLD,
S1, S0,
COD/INTA,
LOCK, HLDA
D15 - D0
RESET
CLK
VSS
VCC
NMI
BUSY
ERROR
INTR
80C286
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