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参数资料
| 型号： | DDP3315CQA |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 15/62页 |
| 文件大小： | 1746K |
| 代理商： | DDP3315CQA |
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ADVANCE INFORMATION
22
Micronas
3. Serial Interface
3.1. I2C-Bus Interface
Communication between the DDP 3315C and the
external
controller
is
done
via
I2C-bus.
The
DDP 3315C has an I2C-bus slave interface and uses
I2C clock synchronization to slow down the interface if
required.
Basically there are two classes of registers in the
DDP 3315C.
The first class are directly addressable I2C registers.
They are embedded in the hardware. These registers
are 8 or 16 bits wide.
The second class are “XDFP-REGISTERS”, which are
used by the “XDFP” onchip controller. These registers
are all 16 bits wide and support read/write operation.
Communication with these registers requires I2C pack-
ets with a 16 bit XDFP-register address and 16 bit
data.
Communication with both classes of registers (I2C and
XDFP-REGISTERS) are performed via I2C. The for-
mat of the I2C telegram depends on which type of reg-
ister is being accessed.
The I2C-bus chip address of the DDP 3315C is given
below:
Note: The I2C address is subject to change.
3.2. I2C Control and Status Registers
The I2C-bus interface uses one level of subaddress.
First the bus address selects the IC, then a subad-
dress selects one of the internal registers. They have 8
or 16-bit data size; 16-bit registers are accessed by
reading/writing two 8-bit data words. Writing is done by
sending the device address first followed by the sub-
address byte and one or two data bytes. For reading,
the read address has to be transmitted first by sending
the device write address followed by the subaddress a
second start condition with the device read address
and reading one or two bytes of data. Fig. 3–2 shows
I2C protocol for read and write operations; the read
operation requires an extra start condition and repeti-
tion of the chip address with read command set. Table
isters.
Fig. 3–1: I2C-Bus protocol (MSB first, data must be stable while clock is high)
Fig. 3–2: I2C-Bus protocol
A6
A5
A4
A3
A2
A1
A0
R/W
1000
1011/0
SDA
SCL
1
0
S
P
I2C-Bus Start Condition
I2C-Bus Stop Condition
S
P
=
Nak
Ack
S
1000 101 W Ack
sub-addr.
Ack S
1000 101
Ack
R
high byte data
low byte data
1 or 2 byte data
S
1000 101 W Ack sub-addr.
Ack
Ack P
P
Write to I2C control register :
Read from I2C control register :
Start condition
Stop condition
W
R
Ack
Nak
S
P
=
1 (Read bit)
0 (Write bit)
=
0 (Acknowledge bit from DDP = grey
1 (Not acknowledge bit from Controller = hatched
or Controller = hatched)
indicating an error state from DDP = grey)
or
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