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参数资料
| 型号： | DDP3315CQA |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 34/62页 |
| 文件大小： | 1746K |
| 代理商： | DDP3315CQA |
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ADVANCE INFORMATION
4
Micronas
DDP 3315C
1. Introduction
The DDP 3315C is a mixed-signal single-chip digital
display and deflection processor, designed for high-
quality backend applications in double scan and HDTV
TV sets with 4:3 or 16:9 picture tubes. The interfaces
qualify the IC to be combined with state of the art digi-
tal scan rate converters, as well as analog HDTV
sources. The DDP 3315C contains the entire digital
video component, deflection processing, and all ana-
log interfaces to display the picture on a CRT. The
main features are
Video Processing
– linear horizontal scaling (0.25 ... 4), as well as
nonlinear horizontal scaling “panorama vision”
– dynamic black level expander
– luma sharpness enhancement by dynamic peaking
and luma transient improvement (LTI)
– color transient improvement (CTI)
– programmable RGB matrix
– black stretch, blue stretch, gamma correction via
programmable Non-linear Colorspace Enhancer
(NCE) on RGB
– two analog double scan inputs with fast blank (one
RGB and one RGB/YCrCb/YPrPb selectable)
– average and peak beam current limiter
– automatic picture tube adjustment (cutoff, drive)
Deflection Processing
– scan velocity modulation output
– digital EHT compensation for vertical / east-west
– vertical angle and bow correction
– differential vertical outputs
– vertical zoom via deflection adjustment
– horizontal and vertical protection circuit
– horizontal frequency for VGA/SVGA/1080I
– black switch off procedure
– supports horizontal and vertical dynamic focus
Miscellaneous
– selectable ITU-R 601 4:1:1 / 4:2:2 YCrCb input at
27/32 MHz or double scan ITU-R 656 input at
54 MHz line-locked clock
– crystal oscillator for horizontal safety
– picture frame generator
– hardware for simple 50/60 Hz to 100/120 Hz con-
version (display frequency doubling)
– PQFP80 package, 5 V analog and 3.3 V digital sup-
ply
Fig. 1–1: Block diagram of the DDP 3315C
E/W
SVM
R
G
B
FB
L
R
G
B
R
G
B
Pr
Y
Pb
FBL
Input
LLC
27/32/
54 MHz
R
G
B
R
G
B
R
G
B
R
G
B
Y
Cb
Cr
Y
Cb
Cr
Output
Cb
Y
Cr
Y /
656 YCrCb
CrCb
4:2:2 /
4:1:1
Sense
Input
E/W
VERT+
VERT
HOUT
V
EW
H
V
EW
H
V
H
V
H
SDA
SCL
PWM 1/2
2H / 2V
(1H / 1V)
FIFO
Controlling
HFLB
DFVBL
PWMV
VPROT
HSAFETY
Clock
Genera-
tor
SVM
Input
Interface
Upcon-
version /
scaling
Picture
Improve-
ment
Matrix /
PFG /
NCE
Video
DAC
analog
RGB-
Matrix
Analog
RGB
Switch
Tube
Control
H&V
Security
Unit
H/V
dynamic
focus
Sawtooth /
Parabola
Generation
H-Drive
Generation
Display-
Freq.
Doubling
EHT
Sync
Pro-
cessing
I2C
Interface
general
purpose
PWM
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