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参数资料
| 型号： | DDP3315CQA |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 29/62页 |
| 文件大小： | 1746K |
| 代理商： | DDP3315CQA |
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ADVANCE INFORMATION
Micronas
35
Timing
14B
bit[8:0]
0
511
start point of active video relative to incoming HS signal in
steps of 2 LLC2 clocks; can be used e.g. for panning
0SFIF
160
vertical blanking stop
bit[8:0]
0
511
last line of vertical blanking
22
VBSO
164
vertical blanking start
bit[8:0]
0
511
first line of vertical blanking (+ 128 offset)
182
VBST
172
bit[10:0]
0
1295
bit[10:0] 0..1295 start of the line in respect to the pixel
counter 90 < (POFS2+NEWLIN)
(3/2xSFIF)< 580
330
NEWLIN
173
bit[10:0]
0
1295
horizontal blanking start
253
HBST
174
bit[10:0]
0
1295
horizontal blanking stop
331
HBSO
178
bit[10:0]
0
1295
start of dynamic focus pulse
0
DFHB
179
bit[10:0]
0
1295
stop of dynamic focus pulse
0
DFHE
bit[12:11]
0
1
2
3
H-pulse vert. blanked
H-pulse
V-pulse
not used
0HDF
Horizontal Deflection
171
bit[5:0]
20
35
horizontal drive pulse duration (high time)
30
HDRV
17D
bit[9]
0
1
high/low active HS input
0
HSYPOL
180
horizontal deflection control register
HCTRL
bit[0]
0
reserved, set to "0"
0
bit[1]
0
1
enable/disable vertical protection
0
VPROT_DIS
bit[2]
0
1
enable/disable h-safety protection
0
HPROT_DIS
bit[3]
0
1
disable/enable drive high during flyback
0
EFLB
bit[4]
1
start ramp up/down
0
RAMP_EN
bit[7:5]
000
001
010
100
110
horizontal frequency H-Freq pixels per line @LLC
in kHz
27 MHz
32 MHz
31.25
864
1024
35.1
768
912
31.46
858
1024
33.8
800
944
37.9
712
844
0HFREQ
181
bit[15:1]
600 600
adjustable delay of PLL2, clamping, and blanking (relative
to incoming hsync) adjust clamping pulse for analog RGB
input; 1 step = 1 pixel clock
5POFS2
182
bit[15:1]
600 600
adjustable delay of flyback, H/VSYNC and analog RGB
(relative to PLL2) adjust horizontal drive or H/VSYNC; 1
step = 1 pixel clock
0POFS3
183
bit[14:6]
0
511
proportional coefficient PLL2, c*2^
9
184
PKP2
185
bit[14:6]
0
511
proportional coefficient PLL3, c*2^
9
102
PKP3
Table 3–5: XDFP Control and Status Registers in Functional Order, continued
Ref
Addr.
(hex)
Bit Slice
Min.
Max.
Function
Default
Register Name
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