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参数资料
| 型号： | DDP3315CQA |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 8/62页 |
| 文件大小： | 1746K |
| 代理商： | DDP3315CQA |
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ADVANCE INFORMATION
16
Micronas
2.2.5. Average Beam Current Limiter
The average beam current limiter (BCL) works on both
the digital YCrCb input and the inserted analog RGB
signals by using either the sense input or the RSW1
input for the beam current measurement. The BCL
uses a different filter to average the beam current dur-
ing the active picture resulting in a 12-bit resolution.
The filter bandwidth is approximately 4 kHz.
The beam current limiter allows the setting of a thresh-
old current, a gain and an additional time constant. If
the beam current is above the threshold, the excess
current is low-pass filtered with the according gain and
time constant. The result is used to attenuate the RGB
outputs by adjusting the white drive multipliers for the
internal (digital) RGB signals, and the analog contrast
multipliers for the analog RGB inputs, respectively.
The lower limit of the attenuator is programmable, thus
a minimum contrast can always be set. If the minimum
contrast is reached, the brightness will be decreased
to a programmable minimum as well. Typical charac-
teristics of the BCL for different loop gains are shown
in Fig. 2–14; for this example the tube has been
assumed to have square law characteristics.
Fig. 2–14: Beam current limiter characteristics:
beam current output vs. drive
2.3. Synchronization and Deflection
2.3.1. Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–15). This block
contains two numeric phase-locked loops and a secu-
rity unit:
– PLL2 generates the horizontal and vertical timing,
e.g. blanking, clamping and sync signals. Phase
and frequency are synchronized by the incoming
sync signals.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal out-
put stage.
– The security unit observes the H-Drive output sig-
nal. With an external 5 MHz reference clock this unit
controls the H-drive “off time” and period. In case of
an incorrect H-drive signal the security unit gener-
ates a free running h-drive signal divided down from
the 5 MHz reference clock.
The DDP 3315C is able to synchronize to various hori-
zontal frequencies, even VGA frequencies. Supported
horizontal input frequencies are listed in Table 2–6.
2.3.2. Security Unit for H-Drive
The security unit observes the H-Drive output signal
with an external 5 MHz reference clock. For different
horizontal frequencies the security unit uses different
ranges to control the H-Drive signal. Selecting a spe-
cific horizontal frequency via I2C-Register HFREQ,
automatically switches to the corresponding security
range. The control ranges are listed in Table 2–6.
The window of the control range has to lie within a
main control window which is selectable with the
FREQSEL input pin. With a low signal at this pin the
main control range is 28.8... 34.4
s and with a high
signal the main control range is 25.6... 29.2
s.
This is to prevent male functions if the horizontal
deflection stage is prepared for VGA frequencies.
The Horizontal Drive Output can be forced to the high
level during Flyback. This means, the falling edge of
the drive pulse is earliest possible at the end of the fly-
back pulse. This function can be enabled via the I2C
bus (EFLB).
be
am
c
u
rr
ent
drive
gain = 0%
gain = 10%
gain = 60%
gain = 90%
threshold
11.5
2
1
1.5
2
3
5
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