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参数资料
| 型号： | DDP3315CQA |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 45/62页 |
| 文件大小： | 1746K |
| 代理商： | DDP3315CQA |
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ADVANCE INFORMATION
Micronas
5
1.1. System Architecture
Fig. 1–1 shows the block diagram of the DDP 3315C.
A clock generator converts different external line
locked clock rates to a common internal sample rate of
~40 MHz, in order to provide a higher horizontal reso-
lution. The input interface accepts ITU-R 601 at 27 or
32 MHz and ITU-R 656 with encoded or external sync
at 54 MHz. The horizontal scaler is used for the scan
rate conversion and for the nonlinear aspect ratio con-
version as well.
For the picture improvement, luma and chroma are
processed separately. The luminance contrast ratio
can be extended with a dynamic black level expander.
In addition the frequency characteristic is improved by
a transient improvement (LTI) and an adaptive
dynamic peaking circuit. The peaking adapts to small
AC amplitudes of high frequency parts, while large AC
amplitudes are processed by the LTI. The chroma sig-
nal is enhanced with a transient improvement (CTI)
with proper limitation to avoid wrong colors.
The full programmable RGB matrix covers control of
color saturation and temperature. A digital white drive
control is used to adjust the white balance and for the
beam current limitation to prevent the CRT from over-
load. A non-linear colorspace enhancer (NCE) for
RGB gives full flexibility for any amplitude characteris-
tic.
High speed10-bit D/A converters are used to convert
digital RGB to analog signals. Separate 9-bit D/A con-
verters control brightness and cutoff. For picture tubes
equipped with an appropriate yoke a scan velocity
modulation (SVM) signal is calculated using a differen-
tiated luminance signal.
Two analog sources can be inserted in the main RGB,
controlled by separate fastblank (FBL) signals. Con-
trast and brightness are adjusted separately from main
RGB. One input is dedicated to RGB for on screen dis-
play (OSD). The second input is processed with an
analog RGB matrix to insert YCbCr/YPbPr or RGB with
control of color saturation and programmable half con-
trast. The bandwidth of ~30 MHz guarantees pixel
based graphics to be displayed with full accuracy.
All previously mentioned features are implemented in
dedicated hardware. An integrated processor controls
the horizontal and vertical deflection, tube measure-
ment loops and beam current limitation. It is also used
to calculate an amplitude histogram of the displayed
image.
The horizontal deflection is synchronized with two
numeric phase-locked loops (PLL) to the incoming
sync. One PLL generates the horizontal timing signals,
e.g. blanking and key-clamping. The second PLL
adjusts the phase of the horizontal drive pulse with a
subpixel accuracy less than 1 ns.
Vertical deflection and east/west correction waveforms
are calculated as 6th order polynomials. This allows
adjustment of an east/west parabola with trapezoidal,
pincushion and an upper/lower corner correction (even
for real flat CRT’s), as well as a vertical sawtooth with
linearity and S-correction. Scaling both waveforms,
and limiting to fix amplitudes, performs a vertical zoom
or compression of the displayed image. A field and line
frequent control loop compensates picture content
depending EHT distortions.
1.2. System Application
To form a complete TV set, the video backend must be
complemented with additional components. Due to the
flexible architecture of the DDP, it can be placed in
various environments (see Fig. 1–2). Applications to
display digital MPEG or PC graphics on large screens,
inserting analog VGA sources in a TV as well as mem-
ory based image processing for 100/120 Hz or pro-
gressive scan rate conversion of TV sources, are
intended with the DDP.
Fig. 1–2: DDP 3315C applications
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CVBS
VPC
323xD
VPC
323xD
CVBS
RGB
SDA
9400/1
DDP
3315C
RGB
H/V
Defl.
OSD, VGA, 1080l
VSP
940x
CVBS
RGB / VGA
DDP
3315C
RGB
H/V
Defl.
OSD, 1080l
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