- 您现在的位置：买卖IC网 > PDF目录381697 > DDRSDRAM1111 (SAMSUNG SEMICONDUCTOR CO. LTD.) DDR SDRAM Specification Version 1.0 PDF资料下载
参数资料
| 型号： | DDRSDRAM1111 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 1.0 |
| 中文描述： | DDR SDRAM的规范版本1.0 |
| 文件页数： | 11/53页 |
| 文件大小： | 669K |
| 代理商： | DDRSDRAM1111 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页
- 11 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
2.2 Input/Output Function Description
Table 3. Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
CKE
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
CS
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
RAS, CAS, WE
Input
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
LDM,(U)DM
Input
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-
ing. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
BA0, BA1
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-
CHARGE command is being applied.
A [n : 0]
Input
Address Inputs : Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address
inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1
define which mode register is loaded during the MODE REGISTER SET command (MRS or
EMRS).
DQ
I/O
Data Input/Output : Data bus
LDQS,(U)DQS
I/O
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
QFC
Output
FET Control : Optional. Output during every Read and Write access. Can be used to control
isolation switches on modules.
NC
-
No Connect : No internal electrical connection is present.
V
DD
Q
Supply
DQ Power Supply : +2.5V
±
0.2V.
V
SS
Q
Supply
DQ Ground.
V
DD
Supply
Power Supply : +2.5V
±
0.2V (device specific).
V
SS
Supply
Ground.
V
REF
Input
SSTL_2 reference voltage.
相关PDF资料 |
PDF描述 |
|---|---|
| DDRSDRAM | DDR SDRAM Specification Version 0.61 |
| DDTA113TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA114TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA115TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA123TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DDR-SJE-Q2 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-Q2R-1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-R1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-R2 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJS-R1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED AlInGaP |
发布紧急采购，3分钟左右您将得到回复。