- 您现在的位置：买卖IC网 > PDF目录381697 > DDRSDRAM1111 (SAMSUNG SEMICONDUCTOR CO. LTD.) DDR SDRAM Specification Version 1.0 PDF资料下载
参数资料
| 型号： | DDRSDRAM1111 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 1.0 |
| 中文描述： | DDR SDRAM的规范版本1.0 |
| 文件页数： | 16/53页 |
| 文件大小： | 669K |
| 代理商： | DDRSDRAM1111 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页
- 16 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
Mode Register Set
*1 : MRS can be issued only at all bank precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
Command
2
0
1
5
3
4
8
6
7
t
CK
2 Clock min.
Precharge
All Banks
Mode
Register Set
t
RP
*2
*1
Any
Command
CK
CK
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address(A2, A1, A0)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
Sequential Mode
Interleave Mode
2
0, 1
1, 0
0, 1
1, 0
4
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and
upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon
exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support
a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the
normal drive strength and weak drive strength will be included in a future revision of this document.
Table 4. Burst address ordering for burst length
Figure 6. Mode Register Set sequence
相关PDF资料 |
PDF描述 |
|---|---|
| DDRSDRAM | DDR SDRAM Specification Version 0.61 |
| DDTA113TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA114TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA115TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA123TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DDR-SJE-Q2 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-Q2R-1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-R1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-R2 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJS-R1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED AlInGaP |
发布紧急采购，3分钟左右您将得到回复。