参数资料
型号: DDRSDRAM1111
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR SDRAM Specification Version 1.0
中文描述: DDR SDRAM的规范版本1.0
文件页数: 44/53页
文件大小: 669K
代理商: DDRSDRAM1111
- 44 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
8.2 AC Timming Parameters & Specifications
Parameter
Symbol
K4H281638B
-TCA2 (DDR266A)
Min
65
75
45
20
20
15
2
1
1
7.5
K4H281638B
-TCB0 (DDR266B)
Min
65
75
45
20
20
15
2
1
1
10
7.5
K4H281638B
-TCA0 (DDR200)
Min
70
80
48
20
20
15
2
1
1
10
Unit Note
Max
Max
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tCDLR
tCCD
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
ns
ns
120K
120K
120K
CL=2.0
CL=2.5
15
15
15
15
15
15
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
Data out high impedence time from CK/CK
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS-in high level width
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tHZQ
tDQSS
tWPRES
tWPREH
tDQSH
0.45
-0.75
-0.75
-
0.9
0.4
-0.75
0.75
0
0.25
0.4
0.55
+0.75
+0.75
+0.5
1.1
0.6
+0.75
1.25
0.45
-0.75
-0.75
-
0.9
0.4
-0.75
0.75
0
0.25
0.4
0.55
+0.75
+0.75
+0.5
1.1
0.6
+0.75
1.25
0.45
-0.8
-0.8
-
0.9
0.4
-0.8
0.75
0
0.25
0.4
0.55
+0.8
+0.8
+0.6
1.1
0.6
+0.8
1.25
tCK
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
2
3
0.6
0.6
0.6
tCK
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tDQSL
tDSC
tIS
tIH
tMRD
tDS
tDH
0.4
0.9
0.9
0.9
15
0.5
0.6
1.1
0.4
0.9
0.9
0.9
15
0.5
0.6
1.1
0.4
0.9
1.1
1.1
16
0.6
0.6
1.1
tCK
tCK
ns
ns
ns
ns
ns
0.5
0.5
0.6
DQ & DM input pulse width
Power down exit time
Exit self refresh to write command
tDIPW
tPDEX
tXSW
1.75
10
95
1.75
10
2
ns
ns
ns
10
116
相关PDF资料
PDF描述
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