参数资料
型号: DR-TRC105-450-EV
厂商: RFM
文件页数: 27/67页
文件大小: 0K
描述: BOARD EVALUATION 450MHZ RFM RFIC
标准包装: 1
类型: 收发器
频率: 447MHz ~ 451MHz
适用于相关产品: TRC105
已供物品: 2 个板,天线,电池
Figure 20 shows the timing diagram for a single byte write sequence to the TRC105 through the SPI configuration
interface. Note that nSS_CONFIG must remain low during the transmission of the two bytes (address and data). If
it goes high after the first byte, then the next byte will be considered as an address byte. When writing to more
than one register successively, nSS_CONFIG does not need to have a high-to-low transition between two write
sequences. The bytes are alternatively considered as an address byte followed by a data byte.
The read sequence through the SPI configuration interface is similar to the write sequence. The host microcon-
troller sends the address during the first SPI communication and then reads the data during a second SPI com-
munication. Note that 0 bits can be input to the SDI during the second SPI communication for a single byte read.
Figure 21 shows the timing diagram for a single byte read sequence from the TRC105 through the SPI.
Figure 21
Figure 22
Multiple configuration register reads are also possible by sending a series of register addresses into the SPI port,
as shown in Figure 22.
3.11 SPI Data FIFO Interface
When the transceiver is used in Buffered or Packet data mode, data is written to and read from the FIFO through
the SPI interface. Two interrupts, IRQ0 and IRQ1, are used to manage the transfer procedure.
When the transceiver is operating in Buffered or Packet data mode, the FIFO interface is selected when
nSS_DATA is set to 0 and nSS_CONFIG is set to 1. SPI operations with the FIFO are similar to operations with
the configuration registers with two important exceptions. First, no addresses are used with the FIFO, only data
bytes are exchanged. Second, nSS_DATA must be toggled high and back low between data bytes when writing
to the FIFO or reading from the FIFO. Toggling nSS_DATA indexes the access pointer to each byte in the FIFO in
lieu of using explicit addressing. Figure 23 shows the timing diagram for a multiple-byte write sequence to the
TRC105 during transmit, and Figure 24 shows the timing for a multi-byte read sequence.
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Page 27 of 67
TRC105 - 05/29/13
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