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参数资料
| 型号： | DR-TRC105-450-EV |
| 厂商： | RFM |
| 文件页数： | 59/67页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 450MHZ RFM RFIC |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 频率： | 447MHz ~ 451MHz |
| 适用于相关产品： | TRC105 |
| 已供物品： | 2 个板，天线，电池 |
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8. In transmit mode, IRQ0 will flag when the FIFO is empty.
9. Set IRQCFG0D bit 3 to 1. IRQ1 will flag when the last bit starts to be transmitted.
10. Load the operating frequency into register set MCFG06 - MCFG08 or MCFG09 - MCFG0B.
11. Select the register set to use by setting MCFG05 bit 0. A 0 value selects register set MCFG06 - MCFG08
and a 1 value selects register set MCFG09 - MCFG0B .
12. When ready to transmit, place the TRC105 in synthesizer mode by setting MCFG00 bits 7..5 to 010. Mon-
itor the TRC105 Pin 23 to confirm PLL lock.
13. Place TRC105 in transmit mode by setting MCFG00 bits 7..5 set to 100.
14. Load the message in the FIFO through the SPI port. In Buffered data mode, the transmitted message
must include the 1-0-1- 0… training preamble, the start pattern and the data. A length byte at the begi n-
ning of the data or a designated end-of-message character is normally used to indicate message length.
15. Monitor IRQ1. It sets when the when the last bit starts to be transmitted. Allow one bit period for the last
bit to be transmitted and then switch to standby mode by setting MCFG00 bits 7..5 to 001.
16. To prepare for receive mode, write a 1 to IRQCFG0E bit 6. This arms the start pattern detection.
17. Switch the TRC105 from standby mode to synthesizer mode by setting MCFG00 bits 7..5 set to 010.
Monitor the TRC105 Pin 23 to confirm PLL lock.
18. Switch from synthesizer mode to receive mode by setting MCFG00 bits 7..5 to 011.
19. Following a start pattern detection, the FIFO will start filling. Note that the preamble and start pattern are
not loaded in the receive FIFO.
20. As each data byte is loaded into the FIFO, IRQ0 will pulse to alert the host microcontroller to retrieve
the byte.
21. The host microcontroller can use a countdown on the length byte or detection of the end-of-message byte
to determine when all of the message data has been retrieved.
22. As soon as all the message has been retrieved, switch the TRC105 to standby mode by setting MCFG00
bits 7..5 to 001.
23. From standby mode, enter another transmit cycle as outlined in steps 12 through 15, or enter another re-
ceive cycle as outlined in steps 16 through 23.
It is possible to transmit messages longer than the FIFO in Buffered data mode by monitoring the nFIFOEMPY
flag and immediately loading additional data bytes. However, messages sent by low power radios such as the
TR103 are normally 127 bytes or less to reduce the chances of corruption due to noise, fading or interference.
6.6.3 Packet Data Mode
The Packet data mode is built on top of the Buffered data mode, and adds a number of standard and optional fea-
tures:
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Fixed or variable length packet options
Generation of preamble and start pattern (network ID) in transmit mode
DC-balancing of data by scrambling (whitening) or Manchester encoding
Generation of a 16-bit error detection CRC
Optional 1-byte node address and/or 1-byte length address
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 59 of 67
TRC105 - 05/29/13
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| DRTU06D06 | 功能描述:时间延迟和计时继电器 180-240VAC/DC 1-60VDC 6A RoHS:否 制造商:Crydom 显示器类型:Hand Dial 电源电压:280 VAC 定时范围: 触点形式: 触点额定值:6 A 端接类型:DIN Rail |
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| DRTU24A06R | 功能描述:时间延迟和计时继电器 90-140VAC/DC 24-280VAC 6A RoHS:否 制造商:Crydom 显示器类型:Hand Dial 电源电压:280 VAC 定时范围: 触点形式: 触点额定值:6 A 端接类型:DIN Rail |
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