参数资料
| 型号： | DS1863K |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/62页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR DS1863 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 电信，无源光学网络（PON） |
| 已用 IC / 零件： | DS1863 |
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Burst-Mode PON Controller
With Integrated Monitoring
used to prevent the alarms from triggering the TX-F and
FETG outputs. See below for more detail on the TX-F
and FETG outputs.
ADC Timing
There are five analog channels that are digitized in a
round robin fashion in the order shown in Figure 4. The
total time required to convert all five channels is t RR
(see electrical specifications for details).
Right Shifting A/D Conversion Result
If the weighting of the ADC digital reading must con-
form to a Predetermined Full-Scale (PFS) value defined
by a specification, then right shifting can be used to
adjust the PFS analog measurement range while main-
taining the weighting of the ADC results. The DS1863 ’ s
range is wide enough to cover all requirements; when
maximum input value is far short of the FS value, right
shifting can be used to obtain greater accuracy. For
instance, the maximum voltage might be 1/8 of the
specified PFS value, so only 1/8 of the converter ’ s
range is effective over this range. An alternative is to
calibrate the ADC ’ s full scale range to 1/8 the readable
PFS value and use a right-shift value of 3. With this
implementation, the resolution of the measurement has
69h. This is true during the setup of internal calibration
as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the five ADC
alarms and the four QT alarms to select which compar-
isons cause it to assert. In addition, the FETG alarm is
selectable via the TX-F mask to cause TX-F to assert.
All alarms, with the exception of FETG, will only cause
TX-F to remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, soft TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, then it is indi-
cating that the DS1863 is in shutdown, and will require
TX-D, soft TX-D, or cycling power to reset. The ADC
and Quick-trip alarms (with the exception of BIAS MAX)
are ignored for the first 8-10 bias current updates dur-
ing power up. Only enabled alarms will activate TX-F.
The following table shows TX-F as a function of TX-D
and the alarm sources.
TX-F as a Function of TX-D and Alarm
Sources
increased by a factor of 8, and because the result is
digitally divided by 8 by right shifting, the bit weight of
the measurement still meets the standard.
The right shift operation on the A/D converter results is
carried out based on the contents of Right Shift Control
Registers (Table 02h Registers 8Eh to 8Fh) in EEPROM.
Three analog channels: MON1 to MON3 each have 3
bits allocated to set the number of right shifts. Up to 7
V CC > V POA
No
Yes
Yes
Yes
TX-D
X
0
0
1
NON-MASKED
TX-F ALARM
X
0
1
X
TX-F
1
0
1
0
right shift operations are allowed and will be executed
as a part of every conversion before the results are
compared to the high and low alarm levels, or loaded
into their corresponding measurement registers 62h to
NORMAL ADC SAMPLE TIMING
ONE ROUND-ROBIN ADC CYCLE
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the five ADC alarms and the four QT alarms to
select which comparisons cause it to assert. Unlike TX-F,
MON3
TEMP
VCC
MON1
MON2
MON3
TEMP
VCC
t RR
Figure 4. ADC Round-Robin Timing.
If V CC low alarm is set for either the TX-F or FETG output, the Round Robin timing will cycle between only TEMP and V CC .
12
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相关代理商/技术参数 |
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