参数资料
型号: DS1863K
厂商: Maxim Integrated Products
文件页数: 15/62页
文件大小: 0K
描述: KIT EVAL FOR DS1863
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电信,无源光学网络(PON)
已用 IC / 零件: DS1863
Burst-Mode PON Controller
With Integrated Monitoring
V POA
V CC
V POD
SEE RECALL
SEE RECALL
FETG
HIGH
IMPEDANCE
NORMAL
OPERATION
DRIVEN TO
FETG DIR
HIGH
IMPEDANCE
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
DRIVEN TO
FETG DIR
HIGH
IMPEDANCE
SEE*
PRECHARGED
TO 0
RECALLED
VALUE
PRECHARGED
TO 0
RECALLED
VALUE
PRECHARGED
TO 0
Figure 7. DS1863 Digital and Analog Power-On Reset.
DS1863 Memory Map
Memory Organization
The DS1863 features six memory banks that include the
following.
The Lower Memory is addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the Table Select byte. The Table Select Byte deter-
mines which Table (01h – 05h) will be mapped into the
upper memory locations.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as some Alarm and Warning sta-
tus bytes.
Table 02h is a multifunction space that contains
Configuration registers, scaling and offset values,
Passwords, interrupt registers as well as other miscella-
neous control bytes.
Table 03h is strictly user EEPROM that is protected by
a PW2 level password.
Table 04h contains a temperature indexed Look up
Table (LUT) for control of the modulation voltage. The
modulation LUT can be programmed in 2 ° C increments
over the -40 ° C to +102 ° C range. Access to this register
is protected by a PW2 level password.
Table 05h contains another LUT which allows the APC
set point to change as a function of temperature to
compensate for Tracking Error (TE). This TE LUT, has
36 entries that determine the APC setting in 4 ° C win-
dows between -40 ° C to 100 ° C. Access to this register
is protected by a PW2 level password.
Complete detail of each byte ’ s function, as well as
Read/Write permissions for each Byte for each table is
provided in the Register Descriptions sections.
Shadowed EEPROM
Many nonvolatile (NV) memory locations (listed within
the Detailed Register Description section) are actually
Shadowed-EEPROM which are controlled by the SEEB
bit in Table 02h, Byte 80h.
The DS1863 incorporates Shadowed EEPROM memory
locations for key memory addresses that may be re-
written many times. By default the Shadowed EEPROM
Bit, SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB these locations function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time, t WR . Because changes made with SEEB
enabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-up value
is the last value written with SEEB disabled. This func-
tion can be used to limit the number of EEPROM writes
during calibration or to change the monitor thresholds
periodically during normal operation helping to reduce
the number of times EEPROM is written. The Memory
Map description indicates which locations are shad-
owed-EEPROM.
____________________________________________________________________
15
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