参数资料
型号: DS21FF42
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: 27 X 27 MM, BGA-300
文件页数: 111/115页
文件大小: 534K
代理商: DS21FF42
DS21FF42/DS21FT42
95 of 115
24.
TIMING DIAGRAMS
RECEIVE SIDE D4 TIMING Figure 24-1
RECEIVE SIDE ESF TIMING Figure 24-2
12
34
5
6
7
8
9
10
11
12 13
14
15 16
17
18 19
20
21 22
23
24
FRAME#
RSYNC /
RFSYNC
RSYNC
1
2
RSYNC
3
RLCLK
RLINK
4
5
RLCLK
RLINK
6
7
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. ZBTSI mode disabled (RCR2.6 = 0)
5. RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames
6. ZBTSI mode is enabled (RCR2.6 = 1)
7. RLINK data (Z bits) is updated one bit time before odd frames and held for four frames
8. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
FRAME#
1
2345
678
9
10
11
12
1
23
45
RSYNC /
RFSYNC
1
RSYNC
RSYNC2
3
RLCLK
RLINK4
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. RLINK data (Fs - bits) is updated one bit prior to even frames and held for two frames
5. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
相关PDF资料
PDF描述
DS21FF42N DATACOM, FRAMER, PBGA300
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DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
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