参数资料
型号: DS21FF42
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: 27 X 27 MM, BGA-300
文件页数: 60/115页
文件大小: 534K
代理商: DS21FF42
DS21FF42/DS21FT42
49 of 115
SYMBOL
POSITION
NAME AND DESCRIPTION
RCL
IMR1.1
Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
RLOS
IMR1.0
Receive Loss of Sync.
0 = interrupt masked
1 = interrupt enabled
IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
(MSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
RSC
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
IMR2.7
Receive Multiframe.
0 = interrupt masked
1 = interrupt enabled
TMF
IMR2.6
Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
SEC
IMR2.5
One Second Timer.
0 = interrupt masked
1 = interrupt enabled
RFDL
IMR2.4
Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
TFDL
IMR2.3
Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
RMTCH
IMR2.2
Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
RAF
IMR2.1
Receive FDL Abort.
0 = interrupt masked
1 = interrupt enabled
RSC
IMR2.0
Receive Signaling Change.
0 = interrupt masked
1 = interrupt enabled
12.
ERROR COUNT REGISTERS
There are a set of three counters in each framer that record bipolar violations, excessive zeros, errors in
the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters are automatically updated on either one second boundaries
(CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence,
these registers contain performance data from either the previous second or the previous 42 ms. The user
can use the interrupt from the one second timer to determine when to read these registers. The user has a
full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their
相关PDF资料
PDF描述
DS21FF42N DATACOM, FRAMER, PBGA300
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