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参数资料
| 型号： | DS21FF42 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封装： | 27 X 27 MM, BGA-300 |
| 文件页数： | 75/115页 |
| 文件大小： | 534K |
| 代理商： | DS21FF42 |
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DS21FF42/DS21FT42
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16.
CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
The
RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
24 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1 (6C)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2 (6D)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3 (6E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1 - 24
RCBR1.0 - 3.7
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1 (32)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2 (33)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3 (34)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1 - 24
TCBR1.0 - 3.7
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
17.
ELASTIC STORES OPERATION
Each framer in the DS21Q42 contains dual two–frame (386 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or
2.048 MHz). The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within the
framer are fully independent and no restrictions apply to the sourcing of the various clocks that are
applied to them. The transmit side elastic store can be enabled whether the receive elastic store is
相关PDF资料 |
PDF描述 |
|---|---|
| DS21FF42N | DATACOM, FRAMER, PBGA300 |
| DS21FT44N | DATACOM, FRAMER, PBGA300 |
| DS21FT44 | DATACOM, FRAMER, PBGA300 |
| DS21Q352 | DATACOM, PCM TRANSCEIVER, PBGA256 |
| DS21Q354 | DATACOM, PCM TRANSCEIVER, PBGA256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21FF42+ | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FF42N | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FF42N+ | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FF44 | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FF44N | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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