参数资料
型号: DS21FF42
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: 27 X 27 MM, BGA-300
文件页数: 90/115页
文件大小: 534K
代理商: DS21FF42
DS21FF42/DS21FT42
76 of 115
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = 93 Hex)
(MSB)
(LSB)
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
SYMBOL
POSITION
NAME AND DESCRIPTION
TDB8
TDC2.7
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to
stop this bit from being used.
TDB7
TDC2.6
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
TDB6
TDC2.5
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
TDB5
TDC2.4
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
TDB4
TDC2.3
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
TDB3
TDC2.2
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
TDB2
TDC2.1
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
TDB1
TDC2.0
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to
stop this bit from being used.
19.2 LEGACY FDL SUPPORT
19.2.1 Overview
The DS21Q42 maintains the circuitry that existed in the previous generation of Dallas Semiconductor’s
single chip transceivers and quad framers. Section 19.2 covers the circuitry and operation of this legacy
functionality. In new applications, it is recommended that the HDLC controller and BOC controller
described in Section 19.1 be used. On the receive side, it is possible to have both the new HDLC/BOC
controller and the legacy hardware working at the same time.
However this is not possible on the
transmit side since their can be only one source the of the FDL data internal to the device.
19.2.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The
framer will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT* pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2 ms to read this data before it is lost.
If the byte in the RFDL matches either of the bytes
programmed into the RMTCH1 or RMTCH2 registers, then the SR2.2 bit will be set to a one and the
INT* pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to
ignore the FDL or Fs pattern until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than 5 ones should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS21Q42
相关PDF资料
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