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参数资料
型号： DS21FF42
厂商： DALLAS SEMICONDUCTOR
元件分类： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA300
封装： 27 X 27 MM, BGA-300
文件页数： 46/115页
文件大小： 534K
代理商： DS21FF42
DS21FF42/DS21FT42
36 of 115
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)
(LSB)
TESE
ODF
RSAO
TSCLKM
RSCLKM
RESE
PLB
FLB
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR1.7
Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
ODF
CCR1.6
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
RSAO
CCR1.5
Receive Signaling All One’s. This bit should not be enabled
if hardware signaling is being utilized. See Section 14 for
more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSCLKM
CCR1.4
TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSCLKM
CCR1.3
RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
RESE
CCR1.2
Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
PLB
CCR1.1
Payload Loopback.
0 = loopback disabled
1 = loopback enabled
FLB
CCR1.0
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
PAYLOAD LOOPBACK
When CCR1.1 is set to a one, the DS21Q42 will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing
applications. In a PLB situation, the DS21Q42 will loop the 192 bits of payload data (with BPVs
corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6
calculation, and the FDL bits are not looped back, they are reinserted by the DS21Q42. When PLB is
enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK
2. All of the receive side signals will continue to operate normally
3. The TCHCLK and TCHBLK signals are forced low
4. Data at the TSER, and TSIG pins is ignored
5. The TLCLK signal will become synchronous with RCLK instead of TCLK
相关PDF资料
PDF描述
DS21FF42N DATACOM, FRAMER, PBGA300
DS21FT44N DATACOM, FRAMER, PBGA300
DS21FT44 DATACOM, FRAMER, PBGA300
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
相关代理商/技术参数
参数描述
DS21FF42+ 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS21FF42N 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS21FF42N+ 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS21FF44 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS21FF44N 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
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