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参数资料
| 型号： | DS80C400-FNY+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 25/97页 |
| 文件大小： | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 75MHz |
| 连通性： | 1 线，CAN，EBI/EMI，以太网，SIO，UART/USART |
| 外围设备： | 电源故障复位，WDT |
| 输入/输出数： | 64 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | ROM |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
| 配用： | DS80C400-KIT#-ND - EVAL KIT FOR DS80C400 |
| 其它名称： | DS80C400+FNY DS80C400+FNY+ DS80C400+FNY+-ND DS80C400+FNY-ND |
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DS80C400 Network Microcontroller
31 of 97
PIN
NAME
FUNCTION
51
P6.5
P6.1
CE5
Program Memory Chip Enable 5
P6.2
CE6
Program Memory Chip Enable 6
P6.3
CE7
Program Memory Chip Enable 7
P6.4
A20 Program/Data Memory Address 20
P6.5
A21 Program/Data Memory Address 21
P6.6
RXD2 Serial Port 2 Receive
P6.7
TXD2 Serial Port 2 Transmit
50
P6.6
49
P6.7
78
A0
Port 7, I/O. Port 7 can function as either an 8-bit, bidirectional I/O port or the nonmultiplexed A0–A7 signals
(when the MUX pin = 1). The reset condition of Port 7 is all bits at logic 1 through a weak pullup. The logic 1
state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written
to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver,
followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
Port
Alternate Function
P7.0
A0 Program/Data Memory Address 0
P7.1
A1 Program/Data Memory Address 1
P7.2
A2 Program/Data Memory Address 2
P7.3
A3 Program/Data Memory Address 3
P7.4
A4 Program/Data Memory Address 4
P7.5
A5 Program/Data Memory Address 5
P7.6
A6 Program/Data Memory Address 6
P7.7
A7 Program/Data Memory Address 7
77
A1
76
A2
75
A3
74
A4
73
A5
72
A6
71
A7
8
TXClk
Transmit Clock, Input. The transmit clock is a continuous clock sourced from the Ethernet PHY controller. It is
used to provide timing reference for transferring of TX_EN and TXD[3:0] signals from the MAC to the external
Ethernet PHY controller. The input clock frequency of TXClk should be 25MHz for 100Mbps operation and
2.5MHz for 10Mbps operation. For ENDEC operation, TXClk serves the same function, but the input clock
frequency should be 10MHz.
7
TX_EN
Transmit Enable, Output. The transmit enable is an active-high output and is synchronous with respect to the
TXClk signal. TX_EN is used to indicate valid nibbles of data for transmission on the MII pins TXD.3–TXD.0.
TX_EN is asserted with the first nibble of the preamble and remains asserted while all nibbles to be transmitted
are presented on the TXD.3–TXD.0 pins. TX_EN negates prior to the first TXClk following the final nibble of the
frame. TX_EN serves the same function for ENDEC operation.
3
TXD.3
Transmit Data, Output. The transmit data outputs provide 4-bit nibbles of data for transmission over the MII.
The transmit data is synchronous with respect to the TXClk signal. For each TXClk period when TX_EN is
asserted, TXD.3–TXD.0 provides the data for transmission to the Ethernet PHY controller. When TX_EN is
deasserted, the TXD data should be ignored. For ENDEC operation, only TXD.0 is used for transmission of
frames.
4
TXD.2
5
TXD.1
6
TXD.0
10
RXClk
Receive Clock, Input. The receive clock is a continuous clock sourced from the Ethernet PHY controller. It is
used to provide timing reference for transferring of RX_DV, RX_ER, and RXD[3:0] signals from the external
Ethernet PHY controller to the MAC. The input clock frequency of RXClk should be 25MHz for 100Mbps
operation and 2.5MHz for 10Mbps operation. For ENDEC operation, RXClk serves the same function, but the
input clock frequency should be 10MHz.
11
RX_DV
Receive Data Valid, Input. The receive data valid is an active-high input from the external Ethernet PHY
controller and is synchronous with respect to the RXClk signal. RX_DV is used to indicate valid nibbles of data
for reception on the MII pins RXD.3–RXD.0. RX_DV is asserted continuously from the first nibble of the frame
through the final nibble. RX_DV negates prior to the first RXClk following the final nibble. RX_DV serves the
same function for ENDEC operation.
9
RX_ER
Receive Error, Input. The receive error is an active-high input from the external Ethernet PHY controller and is
synchronous with respect to the RXClk signal. RX_ER is used to indicate to the MAC that an error (e.g., a
coding error, or any error detectable by the PHY) was detected somewhere in the frame presently being
transmitted by the PHY. RX_ER has no effect on the MAC while RX_DV is deasserted. RX_ER should be low
for ENDEC operation.
17
RXD.3
Receive Data, Input. The receive data inputs provide 4-bit nibbles of data for reception over the MII. The
receive data is synchronous with respect to the RXClk signal. For each RXClk period when RX_DV is asserted,
RXD.3–RXD.0 have the data to be received by the MAC. When RX_DV is deasserted, the RXD data should be
ignored. For ENDEC operation, only RXD.0 is used for reception of frames.
16
RXD.2
15
RXD.1
14
RXD.0
1
CRS
Carrier Sense, Input. The carrier sense signal is an active-high input and should be asserted by the external
Ethernet PHY controller when either the transmit or receive medium is not idle. CRS should be deasserted by
the PHY when the transmit and receive mediums are idle. The PHY should ensure that the CRS signal remains
asserted throughout the duration of a collision condition. The transitions on the CRS signal need not be
synchronous to TXClk or RXClk. CRS serves the same function for ENDEC operation.
2
COL
Collision Detect, Input. The collision detect signal is an active-high input and should be asserted by the
external Ethernet PHY controller upon detection of a collision on the medium. The PHY should ensure that COL
remains asserted while the collision condition persists. The transitions on the COL signal need not be
synchronous to TXClk or RXClk. The COL signal is ignored by the MAC when operating in full-duplex mode.
COL serves the same function for ENDEC operation.
18
MDC
MII Management Clock, Output. The MII management clock is generated by the MAC for use by the external
Ethernet PHY controller as a timing referenced for transferring information on the MDIO pin. MDC is a periodic
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS80C400-FNY+ | 功能描述:8位微控制器 -MCU Network MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| DS80C400-KIT | 功能描述:EVAL KIT FOR DS80C400 RoHS:否 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:- 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| DS80C400-KIT# | 功能描述:开发板和工具包 - 8051 RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
| DS80C410 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C410_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
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