参数资料
型号: DS80C400-FNY+
厂商: Maxim Integrated Products
文件页数: 90/97页
文件大小: 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 75MHz
连通性: 1 线,CAN,EBI/EMI,以太网,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 64
程序存储器容量: 64KB(64K x 8)
程序存储器类型: ROM
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
其它名称: DS80C400+FNY
DS80C400+FNY+
DS80C400+FNY+-ND
DS80C400+FNY-ND
DS80C400 Network Microcontroller
90 of 97
Table 28. Interrupt Summary
NAME
FUNCTION
VECTOR NATURAL
PRIORITY
FLAG BIT
ENABLE BIT
PRIORITY
CONTROL BIT
PFI
Power-Fail Interrupt
33h
0
PFI (WDCON.4)
EPFI (WDCON.5)
N/A
INT0
External Interrupt 0
03h
1
IE0 (TCON.1)
(Note 2)
EX0 (IE.0)
PX0 (IP.0)
TF0
Timer 0
0Bh
2
TF0 (TCON.5)
(Note 1)
ET0 (IE.1)
PT0 (IP.1)
INT1
External Interrupt 1
13h
3
IE1 (TCON.3)
(Note 2)
EX1 (IE.2)
PX1 (IP.2)
TF1
Timer 1
1Bh
4
TF1 (TCON.7)
(Note 1)
ET1 (IE.3)
PT1 (IP.3)
TI0 or RI0
Serial Port 0
23h
5
RI_0(SCON0.0)
ES0 (IE.4)
PS0 (IP.4)
TI_0(SCON0.1)
TF2
Timer 2
2Bh
6
TF2(T2CON.7)
ET2 (IE.5)
PT2 (IP.5)
TI1 or RI1
Serial Port 1
3Bh
7
RI_1(SCON1.0)
ES1 (IE.6)
PS1 (IP.6)
TI_1(SCON1.1)
INT2
External Interrupts 2–5,
1-Wire Bus Master,
Interrupt
43h
8
IE2 (EXIF.4)
EX2-5 (EIE.0)
PX2-5 (EIP.0)
INT3
IE3 (EXIF.5)
INT4
IE4 (EXIF.6)
INT5/OWMI
IE5 (EXIF.7)
(Note 3)
EOWMI (Note 3)
TF3
Timer 3
4Bh
9
TF3 (T3CM.7))
ET3 (EIE.1)
PT3 (EIP.1)
TI2 or RI2
Serial Port 2
53h
10
IE4 (EXIF.6)
ES2 (EIE.2)
PS2 (EIP.2)
WPI
Write Protect Interrupt
5Bh
11
WPIF (MCON2.7)
EWPI (EIE.3)
PWPI (EIP.3)
C0I
CAN0 Interrupt
6Bh
12
Various
C0IE (EIE.6)
C0IP (EIP.6)
EAI
Ethernet Activity
73h
13
TIF (BCUC.5)
EAIE (EIE.5)
EAIP (EIP.5)
RIF (BCUC.4)
WDTI
Watchdog Timer
63h
14
WDIF (WDCON.3)
EWDI (EIE.4)
PWDI (EIP.4)
EPMI
Ethernet Power Mode
7Bh
15
EPMF (BCUC.6)
EPMIE (EIE.7)
EPMIP (EIP.7)
Unless marked, all flags must be cleared by the application software.
Note 1: Cleared automatically by hardware when the service routine is entered.
Note 2: If edge-triggered, the flag is cleared automatically by hardware when the service routine is entered. If level-triggered, the flag follows the
state of the interrupt pin.
Note 3: The global 1-Wire interrupt-enable bit (EOWMI) and individual 1-Wire interrupt source enables are located in the internal 1-Wire bus
master interrupt enable register, and must be accessed through the OWMAD and OWMDR SFRs. Individual 1-Wire interrupt source
flag bits that are located in the internal 1-Wire bus master Interrupt flag register are accessed in the same way.
One’s Complement Adder
The DS80C400 implements a one’s complement adder to support the Internet checksum algorithm. The adder
contains a 16-bit accumulator and is accessed through the one’s complement adder data (OCAD) SFR.
Writing two bytes to the OCAD register initiates a summation between the 16-bit accumulator and the 16-bit value
entered. When entering a new 16-bit value for summation, the MSB should be loaded first and the LSB loaded
second. The calculation begins on the first machine cycle following the second write to the OCAD register and
executes in a single machine cycle. This allows back-to-back writes of 16-bit data to the OCAD register for
summation. The carry out bit from the high-order bit of the calculation is added back into the low-order bit of the
accumulator.
Reading two bytes from the OCAD register downloads the contents of the 16-bit accumulator. When reading the
16-bit accumulator through the OCAD register, the MSB is unloaded first and the LSB is unloaded second. The 16-
bit accumulator is cleared to 0000h following the second read of the OCAD SFR.
The following is an example sequence for producing an Internet checksum for transmission.
Read OCAD twice to make certain that the 16-bit accumulator = 0000h
Write MSB of 16-bit value to OCAD
Write LSB of 16-bit value to OCAD
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