参数资料
型号: DS80C400-FNY+
厂商: Maxim Integrated Products
文件页数: 59/97页
文件大小: 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 75MHz
连通性: 1 线,CAN,EBI/EMI,以太网,SIO,UART/USART
外围设备: 电源故障复位,WDT
输入/输出数: 64
程序存储器容量: 64KB(64K x 8)
程序存储器类型: ROM
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
其它名称: DS80C400+FNY
DS80C400+FNY+
DS80C400+FNY+-ND
DS80C400+FNY-ND
DS80C400 Network Microcontroller
62 of 97
Address Check Block
The address check block of the Ethernet controller monitors the destination address of all incoming packets and
determines whether the address passes or fails the filter criteria configured by CPU. The outcome of this address
filter test, along with bits signaling whether the frame is a broadcast or multicast frame, is reported by the BCU in a
packet’s receive status word.
All incoming frames can be classified as one of three types: unicast, multicast, or broadcast (a special type of
multicast). A unicast frame contains a 0 in the first received bit of the destination address and is intended for a
single node on the network. A multicast frame contains a 1 in the first received bit of the destination address and is
intended for multiple devices on the network. A broadcast frame is a multicast frame containing all 1’s in the
destination address field and is intended for all network devices. Unless specifically disabled through the disable
broadcast frame (DBF) bit in the CSR MAC control register (00h), broadcast frames are always received by the
DS80C400 MAC.
The address filter criteria is established using five bits found in the CSR MAC control register (00h). Three basic
filter possibilities exist: perfect, inverse, and hash. Perfect filtering requires that the destination address perfectly
match the MAC physical address that has been assigned in CSR registers MAC address high (04h) and MAC
address low (08h). Inverse filtering requires that the destination address be anything other than the assigned MAC
physical address. Perfect and inverse filtering are only applied to unicast frames. Hash filtering uses a user-defined
hash table contained in CSR registers multicast address high (0Ch) and multicast address low (10h) to detect a
successful address match. Figure 7 shows the five bits controlling the destination address filter. Table 15 gives the
valid bit combinations and resultant filter modes. Note that some of the address filter mode control bits can instruct
the address check block to automatically pass or fail certain types of frames.
Figure 7. Address Filter Mode Control Bits
CSR Register MAC Control (00h)
31
0
HP (MAC Control.13) Hash/Perfect Filtering Mode
HO (MAC Control.15) Hash-Only Filtering Mode
IF (MAC Control.17) Inverse Filtering
PR (MAC Control.18) Promiscuous Mode
PM (MAC Control.19) Pass All Multicast
Table 15. Address Filter Modes
FILTER MODE CONTROL BITS
DESTINATION ADDRESS FILTER CRITERIA
PM
PR
IF
HO
HP
UNICAST
MULTICAST
0
PERFECT
FAIL
0
1
0
INVERSE
FAIL
0
1
PERFECT
HASH
1
0
x
PERFECT
PASS
0
1
HASH
1
0
1
HASH
PASS
x
1
0
x
PASS (reset default state = 01000b)
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