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参数资料
| 型号： | E28F200BX-B60 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 128K X 16 FLASH 12V PROM, 60 ns, PDSO56 |
| 封装： | 20 X 14 MM, TSOP-56 |
| 文件页数： | 11/48页 |
| 文件大小： | 453K |
| 代理商： | E28F200BX-B60 |
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28F200BX-TB 28F002BX-TB
Table 4 Command Definitions
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req’d
8
Operation Address Data Operation Address Data
Read ArrayReset
1
Write
X
FFH
Intelligent Identifier
3
2 4
Write
X
90H
Read
IA
IID
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Erase SetupErase Confirm
2
5
Write
BA
20H
Write
BA
D0H
WordByte Write SetupWrite
2
6 7
Write
WA
40H
Write
WA
WD
Erase SuspendErase Resume
2
Write
X
B0H
Write
X
D0H
Alternate WordByte Write SetupWrite
2
6 7
Write
WA
10H
Write
WA
WD
NOTES
1 Bus operations are defined in Tables 1 2 3
2 IA e Identifier Address 00H for manufacturer code 01H for device code
3 SRD e Data read from Status Register
4 IID e Intelligent Identifier Data
Following the Intelligent Identifier Command two read operations access manufacturer and device codes
5 BA e Address within the block being erased
6 WA e Address to be written
WD e Data to be written at location PA
7 Either 40H or 10H command is valid
8 When writing commands to the device the upper data bus DQ8 – DQ15 e X (28F200BX-only) which is either VCC or
VSS to avoid burning additional current
InvalidReserved
These are unassigned commands It is not recom-
mended that the customer use any command other
than the valid commands specified above Intel re-
serves the right to redefine these codes for future
functions
Read Array (FFH)
This single write command points the read path at
the array If the host CPU performs a CE
OE
controlled read immediately following a two-write se-
quence that started the WSM then the device will
output status register contents If the Read Array
command is given after Erase Setup the device is
reset to read the array A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup
Inteligent Identifier (90H)
After this command is executed the CUI points the
output path to the Intelligent Identifier circuits Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode all
other address inputs are ignored)
Read Status Register (70H)
This is one of the two commands that is executable
while the state machine is operating After this com-
mand is written a read of the device will output the
contents of the status register regardless of the ad-
dress presented to the device
The device automatically enters this mode after pro-
gram or erase has completed
Clear Status Register (50H)
The WSM can only set the Program Status and
Erase Status bits in the status register it can not
clear them Two reasons exist for operating the
status register in this fashion The first is a synchro-
nization The WSM does not know when the host
CPU has read the status register therefore it would
not know when to clear the status bits Secondly if
the CPU is programming a string of bytes it may be
more efficient to query the status register after pro-
gramming the string Thus if any errors exist while
programming the string the status register will return
the accumulated error status
19
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