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参数资料
| 型号： | E28F200BX-T120 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 128K X 16 FLASH 12V PROM, 120 ns, PDSO56 |
| 封装： | 20 X 14 MM, TSOP-56 |
| 文件页数： | 48/48页 |
| 文件大小： | 453K |
| 代理商： | E28F200BX-T120 |
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28F200BX-TB 28F002BX-TB
16 Pin Descriptions for x8 28F002BX
Symbol
Type
Name and Function
A0–A17
I
ADDRESS INPUTS
for memory addresses Addresses are internally latched during
a write cycle
A9
I
ADDRESS INPUT
When A9 is at 12V the signature mode is accessed During this
mode A0 decodes between the manufacturer and device ID’s
DQ0–DQ7
IO
DATA INPUTSOUTPUTS
Inputs array data on the second CE
and WE
cycle
during a program command Inputs commands to the command user interface
when CE
and WE
are active Data is internally latched during the write and
program cycles Outputs array Intelligent Identifier and status register data The
data pins float to tri-state when the chip is deselected or the outputs are disabled
CE
I
CHIP ENABLE
Activates the device’s control logic input buffers decoders and
sense amplifiers CE
is active low CE
high deselects the memory device and
reduces power consumption to standby levels If CE
and RP
are high but not at
a CMOS high level the standby current will increase due to current flow through the
CE
and RP
input stages
RP
I
RESETDEEP POWERDOWN
Provides Three-State control Puts the device in
deep powerdown mode Locks the Boot Block from programerase
When RP
is at logic high level and equals 65V maximum the Boot Block is locked
and cannot be programmed or erased
When RP
e
114V minimum the Boot Block is unlocked and can be programmed
or erased
When RP
is at a logic low level the Boot Block is locked the deep powerdown
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased therefore providing data protection during power
transitions When RP
transitions from logic low to logic high the flash memory
enters the read-array mode
OE
I
OUTPUT ENABLE
Gates the device’s outputs through the data buffers during a
read cycle OE
is active low
WE
I
WRITE ENABLE
Controls writes to the Command Register and array blocks WE
is active low Addresses and data are latched on the rising edge of the WE
pulse
VPP
PROGRAMERASE POWER SUPPLY
For erasing memory array blocks or
programming data in each block
Note
VPP k VPPLMAX memory contents cannot be altered
VCC
DEVICE POWER SUPPLY (5V g10% 5V g 5%)
GND
GROUND
For all internal circuitry
NC
NO CONNECT
Pin may be driven or left floating
DU
DON’T USE PIN
Pin should not be connected to anything
9
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| E28F200BX-T60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
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| E28F200CV-B60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| E28F200CVB80 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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